Z8F012APJ020SG View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8F012APJ020SG

High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F082A Series

Zilog 

Z8 Encore! XP® F082A Series

Product Specification

26

VCC = 3.3 V

VPOR

VVBO

Program

Execution

Voltage

Brown-Out

VCC = 3.3V

Program

Execution

System Clock

Internal RESET

signal

Note: Not to Scale

POR

counter delay

Figure 6. Voltage Brown-Out Reset Operation

The POR level is greater than the VBO level by the specified hysteresis value. This

ensures that the device undergoes a Power-On Reset after recovering from a VBO condi-

tion.

Watchdog Timer Reset

If the device is operating in NORMAL or HALT Mode, the Watchdog Timer can initiate a

System Reset at time-out if the WDT_RES Flash option bit is programmed to 1, i.e., the

unprogrammed state of the WDT_RES Flash option bit. If the bit is programmed to 0, it

configures the Watchdog Timer to cause an interrupt, not a System Reset, at time-out.

The WDT bit in the Reset Status (RSTSTAT) Register is set to signify that the reset was

initiated by the Watchdog Timer.

External Reset Input

The RESET pin has a Schmitt-Triggered input and an internal pull-up resistor. Once the

RESET pin is asserted for a minimum of four system clock cycles, the device progresses

through the System Reset sequence. Because of the possible asynchronicity of the system

clock and reset signals, the required reset duration may be as short as three clock periods

PS022827-1212

PRELIMINARY

Reset Sources

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