Z8F012APJ020SG View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8F012APJ020SG

High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F082A Series

Zilog 

Z8 Encore! XP® F082A Series

Product Specification

50

Port A–D Pull-up Enable Subregisters

The Port A–D Pull-up Enable Subregister, shown in Table 26, is accessed through the Port

A–D Control Register by writing 06H to the Port A–D Address Register. Setting the bits in

the Port A–D Pull-up Enable subregisters enables a weak internal resistive pull-up on the

specified port pins.

Table 26. Port A–D Pull-Up Enable Subregisters (PxPUE)

Bit

Field

RESET

R/W

Address

7

6

5

4

3

2

1

0

PPUE7 PPUE6 PPUE5 PPUE4 PPUE3 PPUE2 PPUE1 PPUE0

00H (Ports A-C); 01H (Port D); 04H (Port A of 8-pin device)

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

If 06H in Port A–D Address Register, accessible through the Port A–D Control Register

Bit

Description

[7:0]

PPUEx

Port Pull-up Enabled

0 = The weak pull-up on the port pin is disabled.

1 = The weak pull-up on the port pin is enabled.

Note: x indicates the specific GPIO port pin number (7–0).

Port A–D Alternate Function Set 1 Subregisters

The Port A–D Alternate Function Set1 Subregister, shown in Table 27, is accessed

through the Port A–D Control Register by writing 07H to the Port A–D Address Register.

The Alternate Function Set 1 subregisters selects the alternate function available at a port

pin. Alternate Functions selected by setting or clearing bits of this register are defined in

the GPIO Alternate Functions section on page 37.

Note: Alternate function selection on port pins must also be enabled as described in the Port A–

D Alternate Function Subregisters section on page 47.

PS022827-1212

PRELIMINARY

GPIO Control Register Definitions

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