Z8F041APJ020EG View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8F041APJ020EG

High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F082A Series

Zilog 

Z8 Encore! XP® F082A Series

Product Specification

67

Bit

7

Field

RESET

0

R/W

R/W

Address

Table 46. IRQ2 Enable Low Bit Register (IRQ2ENL)

6

5

Reserved

0

0

R/W

R/W

4

3

C3ENL

0

0

R/W

R/W

FC8H

2

C2ENL

0

R/W

1

C1ENL

0

R/W

0

C0ENL

0

R/W

Bit

[7:4]

[3]

C3ENL

[2]

C2ENL

[1]

C1ENL

[0]

C0ENL

Description

Reserved

These bits are reserved and must be programmed to 0000.

Port C3 Interrupt Request Enable Low Bit

Port C2 Interrupt Request Enable Low Bit

Port C1 Interrupt Request Enable Low Bit

Port C0 Interrupt Request Enable Low Bit

Interrupt Edge Select Register

The Interrupt Edge Select (IRQES) Register, shown in Table 47, determines whether an

interrupt is generated for the rising edge or falling edge on the selected GPIO Port A input

pin.

Table 47. Interrupt Edge Select Register (IRQES)

Bit

Field

RESET

R/W

Address

7

IES7

0

R/W

6

IES6

0

R/W

5

IES5

0

R/W

4

3

IES4

IES3

0

0

R/W

R/W

FCDH

2

IES2

0

R/W

1

IES1

0

R/W

0

IES0

0

R/W

Bit

Description

[7:0]

IESx

Interrupt Edge Select x

0 = An interrupt request is generated on the falling edge of the PAx input.

1 = An interrupt request is generated on the rising edge of the PAx input.

Note: x indicates the specific GPIO port pin number (0–7).

PS022827-1212

PRELIMINARY

Interrupt Control Register Definitions

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