OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
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OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Interquad Routing (continued)
groups of five lines each. To effectively route nibble-
wide buses, each of these sets of five lines can connect
In the hIQ block in Figure 29, the XH lines from one
to only one of the bits of the nibble for both the XH and
quadrant connect through a CIP to its counterpart in
XL. For example, hIQ0 lines can only connect to the
the opposite quadrant, creating a path that spans the
XH0 and XL0 lines, and the hIQ1 lines can connect
PLC array. Since a passive CIP is used to connect the
two XH lines, a 3-state signal can be routed on the two
XH lines in the opposite quadrants, and then they can
be connected through this CIP.
S In the hIQ block, the 20 hIQ lines span the array in a
horizontal direction. The 20 hIQ lines consist of four
only to the XH1 and XL1 lines, etc. Buffers are provided
for routing signals from the XH and XL lines onto the
hIQ lines and from the hIQ lines onto the XH and XL
lines. Therefore, a connection from one quadrant to
another can be made using only two XH lines (one in
each quadrant) and one interquad line.
ICE hIQ3[4]
D hIQ3[3]
hIQ3[2]
hIQ3[1]
hIQ3[0]
V E hIQ2[4]
hIQ2[3]
hIQ2[2]
hIQ2[1]
E hIQ2[0]
hIQ3[4]
hIQ3[3]
hIQ3[2]
hIQ3[1]
hIQ3[0]
hIQ2[4]
hIQ2[3]
hIQ2[2]
hIQ2[1]
hIQ2[0]
CT DNTINU hIQ1[4]
hIQ1[3]
E hIQ1[2]
hIQ1[1]
O hIQ1[0]
hIQ0[4]
L hIQ0[3]
hIQ0[2]
hIQ0[1]
SE DISC hIQ0[0]
Figure 29. hIQ Block Detail
hIQ1[4]
hIQ1[3]
hIQ1[2]
hIQ1[1]
hIQ1[0]
hIQ0[4]
hIQ0[3]
hIQ0[2]
hIQ0[1]
hIQ0[0]
5-4537(F).r3
Lattice Semiconductor
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