OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
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OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
Special Function Blocks (continued)
ORCA Series 2 FPGAs
CCLK
CCLK
CCLK
A[17:0]
EPROM
D[7:0]
S OE
CE
E PROGRAM
A[17:0]
DOUT
D[7:0]
DO NE
ORCA
SERIES
FPGA
MASTER
VDD
VDD OR
GND
PRGM
M2
M1
M0
INIT
HDC
LDC
RCLK
DIN
DOUT
ORCA
SERIES
FPGA
SLAVE #1
DO NE
PRGM
VDD
M2
M1
M0
INIT
HDC
LDC
RCLK
DIN
DOUT
ORCA
SERIES
FPGA
SLAVE #2
VDD
DONE
PRGM
VDD
INIT
M2
HDC
VDD
M1
LDC
M0
RCLK
VIC D Figure 48. Boundary-Scan Interface
5-4488(F)
E The BSM also increases test throughput with a dedi-
E U cated automatic test-pattern generator and with com-
pression of the test response with a signature analysis
register. The PC-based boundary-scan test card/soft-
D ware allows a user to quickly prototype a boundary-
IN scan test setup.
T T Boundary-Scan Instructions
The ORCA Series boundary-scan circuitry is used for
C N three mandatory IEEE 1149.1 tests (EXTEST, SAM-
PLE/PRELOAD, BYPASS) and four ORCA-deï¬ned
instructions. The 3-bit wide instruction register supports
E the eight instructions listed in Table 12.
L O Table 12. Boundary-Scan Instructions
E C Code
000
001
S IS 010
011
100
D 101
Instruction
EXTEST
PLC Scan Ring 1
RAM Write (RAM_W)
Reserved
SAMPLE/PRELOAD
PLC Scan Ring 2
The external test (EXTEST) instruction allows the inter-
connections between ICs in a system to be tested for
opens and stuck-at faults. If an EXTEST instruction is
performed for the system shown in Figure 47, the con-
nections between U1 and U2 (shown by nets a, b, and
c) can be tested by driving a value onto the given nets
from one device and then determining whether the
same value is seen at the other device. This is deter-
mined by shifting 2 bits of data for each pin (one for the
output value and one for the 3-state value) through the
BSR until each one aligns to the appropriate pin.
Then, based upon the value of the 3-state signal, either
the I/O pad is driven to the value given in the BSR, or
the BSR is updated with the input value from the I/O
pad, which allows it to be shifted out TDO.
The SAMPLE instruction is useful for system debug-
ging and fault diagnosis by allowing the data at the
FPGA’s I/Os to be observed during normal operation.
The data for all of the I/Os is captured simultaneously
into the BSR, allowing them to be shifted-out TDO to
the test host. Since each I/O buffer in the PICs is bidi-
rectional, two pieces of data are captured for each I/O
pad: the value at the I/O pad and the value of the
3-state control signal.
110 RAM Read (RAM_R)
111 BYPASS
Lattice Semiconductor
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