ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

In order to improve overall system performance the DATA phase of the transfer can be DMA assisted. The static

memory embeds a NAND Flash Error Correction Code controller with the features as follows:

 Algorithm based on BCH codes

 Supports also SLC 1-bit (BCH 2-bit), SLC 4-bit (BCH 4-bit)

 Programmable Error Correcting Capability:

̶ 2-bit, 4-bit, 8-bit and 16-bit errors for 512 bytes/sector (4 Kbyte page)

̶ 24-bit error for 1024 bytes/sector (8 Kbyte page)

 Programmable sector size: 512 bytes or 1024 bytes

 Programmable number of sector per page: 1, 2, 4 or 8 blocks of data per page

 Programmable spare area size

 Supports spare area ECC protection

 Supports 8 Kbyte page size using 1024 bytes/sector and 4 Kbyte page size using 512 bytes/sector

 Error detection is interrupt driven

 Provides hardware acceleration for error location

 Finds roots of error-locator polynomial

 Programmable number of roots

32 SAMA5D3 Series [DATASHEET]

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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