SST89E58RD2-33-C-NJ View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
Manufacturer
SST89E58RD2-33-C-NJ Datasheet PDF : 91 Pages
| |||
FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
TABLE 14-10: SERIAL PORT TIMING
Symbol
TXLXL
TQVXH
TXHQX
Parameter
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
TXHDX
TXHDV
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
12MHz
Min Max
1.0
700
50
0
700
Oscillator
40MHz
Variable
Min Max
Min
Max
Units
0.3
12TCLCL
µs
117
10TCLCL - 133
ns
2TCLCL - 117
ns
0
2TCLCL - 50
ns
0
0
ns
117
10TCLCL - 133 ns
T14-10.0 1255
INSTRUCTION
0
ALE
CLOCK
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
CLEAR RI
1
2
3
4
5
6
7
8
TXLXL
TQVXH
0
TXHQX
1
TXHDV
VALID
VALID
2
TXHDX
VALID
3
VALID
4
VALID
5
VALID
6
VALID
7
SET TI
VALID
SET R I
1255 F39.0
FIGURE 14-7: SHIFT REGISTER MODE TIMING WAVEFORMS
VIHT
VHT
VILT
VLT
1255 F40.0
AC Inputs during testing are driven at VIHT (VDD -0.5V) for Logic "1" and
VILT (0.45V) for a Logic "0". Measurement reference points for inputs and
outputs are at VHT (0.2VDD + 0.9) and VLT (0.2VDD - 0.1)
Note: VHT- VHIGH Test
VLT- VLOW Test
VIHT-VINPUT HIGH Test
VILT- VINPUT LOW Test
FIGURE 14-8: AC TESTING INPUT/OUTPUT TEST
WAVEFORM
VLOAD +0.1V
VLOAD
VLOAD -0.1V
Timing Reference
Points
VOH -0.1V
VOL +0.1V
1255 F41.0
For timing purposes, a port pin is no longer floating when a 100 mV
change from load voltage occurs, and begins to float when a 100 mV
change from the loaded VOH/VOL level occurs. IOL/IOH = ± 20mA.
FIGURE 14-9: FLOAT WAVEFORM
©2004 Silicon Storage Technology, Inc.
79
S71255-00-000
3/04
Share Link: 