STM32F207IE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM32F207IE Datasheet PDF : 177 Pages
| |||
STM32F20xxx
Electrical characteristics
Table 66. DAC characteristics (continued)
Symbol
Parameter
Min Typ
Max
Unit
Comments
Integral non linearity
(difference between
-
-
INL(4)
measured value at Code i
and the value at Code i on a
line drawn between Code 0
-
-
and last Code 1023)
Offset error
-
-
Offset(4)
(difference between
measured value at Code
-
-
(0x800) and the ideal value =
VREF+/2)
-
-
Gain
error(4)
Gain error
-
-
Settling time (full scale: for a
10-bit input code transition
tSETTLING(4)
between the lowest and the
highest input codes when
-
3
DAC_OUT reaches final
value ±4LSB
THD(4)
Total Harmonic Distortion
Buffer ON
-
-
Max frequency for a correct
Update
rate(2)
DAC_OUT change when
small variation in the input
-
-
code (from code i to i+1LSB)
Wakeup time from off state
tWAKEUP(4) (Setting the ENx bit in the
DAC Control register)
- 6.5
Power supply rejection ratio
PSRR+ (2) (to VDDA) (static DC
- –67
measurement)
±1
±4
±10
±3
±12
±0.5
LSB
Given for the DAC in 10-bit
configuration.
LSB
Given for the DAC in 12-bit
configuration.
mV
Given for the DAC in 12-bit
configuration
LSB
Given for the DAC in 10-bit at
VREF+ = 3.6 V
LSB
Given for the DAC in 12-bit at
VREF+ = 3.6 V
%
Given for the DAC in 12-bit
configuration
6
µs
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
-
dB
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
1
MS/s
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
10
µs input code between lowest and
highest possible ones.
–40
dB No RLOAD, CLOAD = 50 pF
1. If IRROFF is set to VDD, this value can be lowered to 1.7 V when the device operates in the 0 to 70 °C temperature range.
2. Guaranteed by design, not tested in production.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization, not tested in production.
Doc ID 15818 Rev 9
121/177
Share Link: 