STM32F407ZEH7TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM32F407ZEH7TR Datasheet PDF : 185 Pages
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STM32F405xx, STM32F407xx
Electrical characteristics
Table 35. Main PLL characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fPLL_IN
fPLL_OUT
fPLL48_OUT
PLL input clock(1)
PLL multiplier output clock
48 MHz PLL multiplier output
clock
0.95(2)
1
24
-
-
48
2.10 MHz
168 MHz
75
MHz
fVCO_OUT
tLOCK
PLL VCO output
PLL lock time
192
-
VCO freq = 192 MHz
75
-
VCO freq = 432 MHz
100
-
432 MHz
200
µs
300
RMS -
25
-
Cycle-to-cycle jitter
peak
to
-
±150
-
System clock
peak
120 MHz
RMS -
15
-
Jitter(3)
Period Jitter
peak
to
-
peak
±200
-
ps
Main clock output (MCO) for
RMII Ethernet
Cycle to cycle at 50 MHz
on 1000 samples
-
32
-
Main clock output (MCO) for MII Cycle to cycle at 25 MHz
Ethernet
on 1000 samples
-
40
-
Bit Time CAN jitter
Cycle to cycle at 1 MHz
on 1000 samples
-
330
-
IDD(PLL)(4)
PLL power consumption on VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
IDDA(PLL)(4)
PLL power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design, not tested in production.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Based on characterization, not tested in production.
Table 36. PLLI2S (audio PLL) characteristics
Symbol
Parameter
Conditions
Min Typ
fPLLI2S_IN
fPLLI2S_OUT
fVCO_OUT
tLOCK
PLLI2S input clock(1)
PLLI2S multiplier output clock
PLLI2S VCO output
PLLI2S lock time
VCO freq = 192 MHz
VCO freq = 432 MHz
0.95(2)
1
-
-
192
-
75
-
100
-
Max Unit
2.10 MHz
216 MHz
432 MHz
200
µs
300
DocID022152 Rev 4
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