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STM32F407ZEH7TR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
STM32F407ZEH7TR Datasheet PDF : 185 Pages
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STM32F405xx, STM32F407xx
Electrical characteristics
CPOL = 0
Figure 43. I2S slave timing diagram (Philips protocol)
tc(CK)
CPOL = 1
WS input
SDtransmit
SDreceive
tw(CKH)
tw(CKL)
th(WS)
tsu(WS)
LSB transmit(2)
tsu(SD_SR)
LSB receive(2)
MSB transmit
MSB receive
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
th(SD_ST)
LSB transmit
LSB receive
ai14881b
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 44. I2S master timing diagram (Philips protocol)(1)
tf(CK)
tr(CK)
CPOL = 0
CPOL = 1
WS output
SDtransmit
SDreceive
tc(CK)
tw(CKH)
tv(WS)
tw(CKL)
th(WS)
tv(SD_MT)
LSB transmit(2)
MSB transmit
Bitn transmit
tsu(SD_MR)
LSB receive(2)
MSB receive
th(SD_MR)
Bitn receive
th(SD_MT)
LSB transmit
LSB receive
ai14884b
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
USB OTG FS characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
DocID022152 Rev 4
123/185

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