STM32F405REY7TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F405REY7TR

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

STM32F405xx, STM32F407xx

Electrical characteristics

Table 59. USB OTG FS electrical characteristics(1)

Driver characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

tr

Rise time(2)

tf

Fall time(2)

CL = 50 pF

4

CL = 50 pF

4

20

ns

20

ns

trfm

Rise/ fall time matching

tr/tf

90

110

%

VCRS Output signal crossover voltage

1.3

2.0

V

1. Guaranteed by design, not tested in production.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

USB HS characteristics

Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from

tests performed under the ambient temperature, fHCLK frequency summarized in Table 61

and VDD supply voltage conditions summarized in Table 60, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5VDD.

Refer to Section Section 5.3.16: I/O port characteristics for more details on the

input/outputcharacteristics.

Symbol

Table 60. USB HS DC electrical characteristics

Parameter

Min.(1)

Input level

VDD USB OTG HS operating voltage

2.7

1. All the voltages are measured from the local ground potential.

Max.(1)

3.6

Unit

V

Table 61. USB HS clock timing parameters(1)

Parameter

Symbol

Min Nominal Max Unit

fHCLK value to guarantee proper operation of

USB HS interface

Frequency (first transition)

8-bit ±10% FSTART_8BIT

Frequency (steady state) ±500 ppm

FSTEADY

Duty cycle (first transition)

8-bit ±10% DSTART_8BIT

Duty cycle (steady state) ±500 ppm

DSTEADY

Time to reach the steady state frequency and

duty cycle after the first transition

TSTEADY

Clock startup time after the

de-assertion of SuspendM

Peripheral

Host

PHY preparation time after the first transition

of the input clock

TSTART_DEV

TSTART_HOST

TPREP

30

54

59.97

40

49.975

-

-

-

-

MHz

60

66 MHz

60

60.03 MHz

50

60

%

50 50.025 %

-

1.4

ms

-

5.6

ms

-

-

-

-

µs

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