STM32F405xx, STM32F407xx
Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 52 or Figure 53,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F
V REF+
(See note 1)
1 µF // 10 nF
1 µF // 10 nF
V DDA
V SSA/V REF-
(See note 1)
ai17535
1.
VanRdEFL+QaFnPd1V7R6E. FW– hinepnuVtsRaErFe+baontdh
aVvRaEiFla–balereonnoUt FaBvaGilAab1l7e6, .thVeRyEFa+reisinatlesronaavllyaiclaobnleneocnteLdQtFoPV1D0D0A,
LQFP144,
and VSSA.
Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F
VREF+/VDDA
(See note 1)
1 µF // 10 nF
VREF–/VSSA
(See note 1)
ai17536
1.
VanRdEFL+QaFnPd1V7R6E. FW– hinepnuVtsRaErFe+baontdh
aVvRaEiFla–balereonnoUt FaBvaGilAab1l7e6, .thVeRyEFa+reisinatlesronaavllyaiclaobnleneocnteLdQtFoPV1D0D0A,
LQFP144,
and VSSA.
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