STM32F405OEH6TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F405OEH6TR

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

Electrical characteristics

STM32F405xx, STM32F407xx

Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)

th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK

-

ns

tv(A_NE)

FSMC_NEx low to FSMC_A valid

-

0

ns

tv(NADV_NE) FSMC_NEx low to FSMC_NADV low

1

2

ns

tw(NADV) FSMC_NADV low time

THCLK– 2

THCLK+ 1

ns

th(AD_NADV)

FSMC_AD(address) valid hold time after

FSMC_NADV high)

THCLK–2

-

ns

th(A_NWE)

th(BL_NWE)

tv(BL_NE)

tv(Data_NADV)

th(Data_NWE)

Address hold time after FSMC_NWE high

FSMC_BL hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_NADV high to Data valid

Data hold time after FSMC_NWE high

THCLK

THCLK–2

-

-

THCLK

-

ns

-

ns

1.5

ns

THCLK–0.5 ns

-

ns

1. CL = 30 pF.

2. Based on characterization, not tested in production.

Synchronous waveforms and timings

Figure 59 through Figure 62 represent synchronous waveforms and Table 80 through

Table 82 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

• BurstAccessMode = FSMC_BurstAccessMode_Enable;

• MemoryType = FSMC_MemoryType_CRAM;

• WriteBurst = FSMC_WriteBurst_Enable;

• CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual)

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

In all timing tables, the THCLK is the HCLK clock period (with maximum

FSMC_CLK = 60 MHz).

142/185

DocID022152 Rev 4

Share Link: