STM32F407RGH7 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F407RGH7

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

Electrical characteristics

STM32F405xx, STM32F407xx

Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued)

th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high

0

-

ns

tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high

4

-

ns

th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high

0

-

ns

1. CL = 30 pF.

2. Based on characterization, not tested in production.

Figure 60. Synchronous multiplexed PSRAM write timings

tw(CLK)

tw(CLK)

BUSTURN = 0

FSMC_CLK

FSMC_NEx

td(CLKL-NADVL)

FSMC_NADV

FSMC_A[25:16]

FSMC_NWE

td(CLKL-ADV)

FSMC_AD[15:0]

Data latency = 0

td(CLKL-NExL)

td(CLKL-NADVH)

td(CLKL-AV)

td(CLKL-NWEL)

td(CLKL-ADIV)

td(CLKL-Data)

AD[15:0]

td(CLKL-Data)

D1

td(CLKL-NExH)

td(CLKL-AIV)

td(CLKL-NWEH)

D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

tsu(NWAITV-CLKH)

FSMC_NBL

th(CLKH-NWAITV)

td(CLKL-NBLH)

ai14992g

Table 80. Synchronous multiplexed PSRAM write timings(1)(2)

Symbol

Parameter

Min

Max

tw(CLK)

FSMC_CLK period

2THCLK

-

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)

-

1

td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)

1

-

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low

-

0

td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high

0

-

td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25)

-

0

Unit

ns

ns

ns

ns

ns

ns

144/185

DocID022152 Rev 4

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