STM32F407RGH6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F407RGH6

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

Electrical characteristics

STM32F405xx, STM32F407xx

Table 84. Switching characteristics for PC Card/CF read and write cycles

in I/O space(1)(2)

Symbol

Parameter

Min

Max

tw(NIOWR)

FSMC_NIOWR low width

tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid

th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid

td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid

th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid

td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid

th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid

tw(NIORD)

FSMC_NIORD low width

tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high

td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high

1. CL = 30 pF.

2. Based on characterization, not tested in production.

8THCLK –1

-

8THCLK– 2

-

5THCLK–1.5

-

5THCLK– 1.5

8THCLK–0.5

9

0

-

5THCLK– 1

-

5THCLK+ 2.5

-

5THCLK+ 2

-

-

-

-

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

NAND controller waveforms and timings

Figure 69 through Figure 72 represent synchronous waveforms, and Table 85 and Table 86

provide the corresponding timings. The results shown in this table are obtained with the

following FSMC configuration:

• COM.FSMC_SetupTime = 0x01;

• COM.FSMC_WaitSetupTime = 0x03;

• COM.FSMC_HoldSetupTime = 0x02;

• COM.FSMC_HiZSetupTime = 0x01;

• ATT.FSMC_SetupTime = 0x01;

• ATT.FSMC_WaitSetupTime = 0x03;

• ATT.FSMC_HoldSetupTime = 0x02;

• ATT.FSMC_HiZSetupTime = 0x01;

• Bank = FSMC_Bank_NAND;

• MemoryDataWidth = FSMC_MemoryDataWidth_16b;

• ECC = FSMC_ECC_Enable;

• ECCPageSize = FSMC_ECCPageSize_512Bytes;

• TCLRSetupTime = 0;

• TARSetupTime = 0.

In all timing tables, the THCLK is the HCLK clock period.

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DocID022152 Rev 4

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