STM32F407IGH6TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F407IGH6TR

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

Description

STM32F405xx, STM32F407xx

The device also features an embedded programmable voltage detector (PVD) that monitors

the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be

generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is

higher than the VPVD threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on

reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin.

An external power supply supervisor should monitor VDD and should maintain the device in

reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to

this external power supply supervisor. Refer to Figure 7: Power supply supervisor

interconnection with internal reset OFF.

Figure 7. Power supply supervisor interconnection with internal reset OFF

VDD

External VDD power supply supervisor

Ext. reset controller active when

VDD < 1.7 V or 1.8 V (1)

PDR_ON

NRST

Application reset

signal (optional)

VDD

1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.

MS31383V3

The VDD specified threshold, below which the device must be maintained under reset, is

1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the

0 to 70 °C temperature range.

A comprehensive set of power-saving mode allows to design low-power applications.

When the internal reset is OFF, the following integrated features are no more supported:

• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled

• The brownout reset (BOR) circuitry is disabled

• The embedded programmable voltage detector (PVD) is disabled

• VBAT functionality is no more available and VBAT pin should be connected to VDD

All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset

through the PDR_ON signal.

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DocID022152 Rev 4

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