74V2G70
TRIPLE BUFFER
s HIGH SPEED: tPD = 3.0ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 1µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8mA (MIN) at VCC = 4.5V
IIOH| = IOL = 4mA (MIN) at VCC = 3.0V
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V2G70 is an advanced high-speed CMOS
TRIPLE NOT INVERTED BUFFER fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS tecnology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage.
SOT 23-8L
SOT 323-8L
ORDER CODES
PACKAGE
SOT23-8L
SOT323-8L
T&R
74V2G70STR
74V2G70CTR
This device can be used to interface 5V to 3V
systems and it is ideal for portable applications
like personal digital assistant, camcorder and all
battery-powered equipment.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
November 2001
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