74V2G74STR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

74V2G74STR

SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR

STMicroelectronics 

74V2G74

SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR

s HIGH SPEED:

fMAX = 170 MHz (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 1 µA (MAX.) at TA=25°C

s HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

s POWER DOWN PROTECTION ON INPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 5.5V

s FUNCTION COMPATIBLE WITH

74 SERIES 74

s IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74V2G74 is an advanced high-speed CMOS

SINGLE D-TYPE FLIP FLOP WITH PRESET

AND CLEAR fabricated with sub-micron silicon

gate and double-layer metal wiring C2MOS

tecnology.

A signal on the D INPUT is transfered to the Q and

Q OUTPUTS during the positive going transition

of the clock pulse.

SOT23-8L

SOT323-8L

ORDER CODES

PACKAGE

SOT23-8L

SOT323-8L

T&R

74V2G70STR

74V2G70CTR

CLEAR and PRESET are independent of the

clock and accomplished by a low setting on the

appropriate input.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them ESD immunity and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

December 2001

1/13

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