AD5162BRM2.5-RL7(RevA) View Datasheet(PDF) - Analog Devices
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AD5162BRM2.5-RL7 Datasheet PDF : 20 Pages
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AD5162
SPI INTERFACE
SPI COMPATIBLE 3-WIRE SERIAL BUS
The AD5162 contains a 3-wire SPI compatible digital interface
(SDI, CS, and CLK). The 9-bit serial word must be loaded MSB
first. The format of the word is shown in Table 8.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 42).
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5162 uses a
9-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
Table 8. Serial Data-Word Format
B8
B7 B6 B5 B4 B3 B2 B1 B0
A0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
28
27
20
1
SDI
0
1
CLK
0
1
CS
0
1
VOUT
0
A0 D7 D6 D5 D4 D3 D2 D1 D0
RDAC REGISTER LOAD
Figure 42. SPI Interface Timing Diagram
(VA = 5 V, VB = 0 V, VW = ) VOUT
1
SDI
(DATA IN)
Dx
0
1
tCH
CLK
0
tCSHO
tCSS
1
CS
0
VDD
VOUT
0
Dx
tDS
tCL
tCH
tCS1
tCSH1
tCSW
tS
±1LSB
Figure 43. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = ) VOUT
Rev. A | Page 16 of 20
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