AD5173BRM2.5-RL7(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5173BRM2.5-RL7
(Rev.:RevA)

256-Position One-Time Programmable Dual-Channel I2C Digital Potentiometers

Analog Devices 

AD5172/AD5173

OPERATION

A

SCL

SDA

I2C INTERFACE

DAC

REG.

MUX

DECODER

W

B

COMPARATOR

ONE-TIME

PROGRAM/TEST

CONTROL BLOCK

FUSES

EN

FUSE

REG.

Figure 35. Detailed Functional Block Diagram

The AD5172/AD5173 is a 256-position, digitally controlled

variable resistor (VR) that employs fuse link technology to

achieve memory retention of resistance setting.

An internal power-on preset places the wiper at midscale

during power-on. If the OTP function has been activated, the

device powers up at the user-defined permanent setting.

ONE-TIME PROGRAMMING (OTP)

Prior to OTP activation, the AD5172/AD5173 presets to mid-

scale during initial power-on. After the wiper is set at the

desired position, the resistance can be permanently set by

programming the T bit high along with the proper coding (see

Table 5 and Table 6). Note that fuse link technology requires 6 V

to blow the internal fuses to achieve a given setting. The user is

allowed only one attempt at blowing the fuses. Once program-

ming is completed, the power supply voltage must be reduced to

the normal operating range of 2.7 V to 5.5 V.

The device control circuit has two validation bits, E1 and E0,

that can be read back to check the programming status (see

Table 7). Users should always read back the validation bits to

ensure that the fuses are properly blown. After the fuses have

been blown, all fuse latches are enabled upon subsequent

power-on; therefore, the output corresponds to the stored

setting. Figure 35 shows a detailed functional block diagram.

PROGRAMMING THE VARIABLE RESISTOR AND

VOLTAGE

Rheostat Operation

The nominal resistance of the RDAC between terminals A and

B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal

resistance (RAB) of the VR has 256 contact points accessed by

the wiper terminal, plus the B terminal contact. The 8-bit data

in the RDAC latch is decoded to select one of the 256 possible

settings.

A

W

A

W

A

W

B

B

B

Figure 36. Rheostat Mode Configuration

Assuming a 10 kΩ part is used, the wiper’s first connection

starts at the B terminal for data 0x00. Because there is a 50 Ω

wiper contact resistance, such a connection yields a minimum

of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The

second connection is the first tap point, which corresponds to

139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for data

0x01. The third connection is the next tap point, representing

178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB

data value increase moves the wiper up the resistor ladder until

the last tap point is reached at 10,100 Ω (RAB + 2 × RW).

A

RS

D7

RS

D6

D5

D4

D3

RS

D2

D1

D0

W

RDAC

RS

LATCH

AND

B

DECODER

Figure 37. AD5172/AD5173 Equivalent RDAC Circuit

Rev. A | Page 12 of 24

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