AD5172/AD5173
ESD PROTECTION
All digital inputs—SDA, SCL, AD0, and AD1— are protected
with a series input resistor and parallel Zener ESD structures, as
shown in Figure 39 and Figure 40.
340Ω
LOGIC
GND
Figure 39. ESD Protection of Digital Pins
A,B,W
GND
Figure 40. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5172/AD5173 VDD to GND power supply defines the
boundary conditions for proper 3-terminal digital potentiom-
eter operation. Supply signals present on terminals A, B, and W
that exceed VDD or GND are clamped by the internal forward-
biased diodes (see Figure 41).
VDD
A
W
B
GND
Figure 41. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 41), it is important to
power VDD/GND before applying any voltage to terminals A, B,
and W. Otherwise, the diode will be forward biased such that
VDD is powered unintentionally and may affect the rest of the
user’s circuit. The ideal power-up sequence is GND, VDD, the
digital inputs, and then VA/VB/VW. The relative order of
powering VA, VB, VW, and the digital inputs is not important as
long as they are powered after VDD/GND.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time pro-
gramming and normal operating voltage supplies are applied to
the same VDD terminal of the AD5172/AD5173. The AD5172/
AD5173 employ fuse link technology that requires 6 V to blow
the internal fuses to achieve a given setting. The user is allowed
only one attempt at blowing the fuses. Once programming is
completed, power supply voltage must be reduced to the normal
2.7 V to 5.5 V operating range. Such dual voltage requirements
require isolation between the supplies. The fuse programming
supply (either an on-board regulator or rack-mount power sup-
ply) must be rated at 6 V and must be able to provide a 100 mA
transient current for 400 ms for successful one-time program-
ming. Once programming is complete, the 6 V supply must be
removed to allow normal operation at 2.7 V to 5.5 V at regular
microamp current levels. Figure 42 shows the simplest imple-
mentation using a jumper. This approach saves one voltage
supply, but draws additional current and requires manual
configuration.
6V
R1 50kΩ
CONNECT J1 HERE
FOR OTP
C1
C2
5V 1µF 1nF
R2 250kΩ
CONNECT J1 HERE
AFTER OTP
VDD
AD5172/
AD5173
Figure 42. Power Supply Requirement
An alternate approach in 3.5 V to 5.5 V systems adds a signal
diode between the system supply and the OTP supply for
isolation, as shown in Figure 43.
6V
3.5V–5.5V
APPLY FOR OTP ONLY
D1
C1
C2
1µF 1nF
VDD
AD5172/
AD5173
Figure 43. Isolate 6 V OTP Supply from 3.5 V to 5.5 V Normal Operating
Supply. The 6 V supply must be removed once OTP is completed.
Rev. A | Page 14 of 24