AD5280BRU200 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5280BRU200

15 V, I2C Compatible 256-Position Digital Potentiometers

Analog Devices 

AD5280/AD5282

t8

SDA

t1

t8

t9

t6

SCL

t2

P

S

t3

t4

t7

t5

S

Figure 1. Detailed Timing Diagram

t10

P

Data of AD5280/AD5282 is accepted from the I2C bus in the following serial format:

S 0 1 0 1 1 AD1 AD0 R/W A A/B RS SD O1 O2 X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P

Slave Address Byte

Instruction Byte

Data Byte

Where:

S = Start Condition

P = Stop Condition

A = Acknowledge

A = No Acknowledge

X = Don’t Care

AD1, AD0 = Package Pin Programmable Address Bits

R/W = Read Enable at High and Write Enable at Low

A/B = RDAC Subaddress Select. “Zero” for RDAC1 and “One” for RDAC2

RS = Midscale Reset, Active High (only affects selected channel)

SD = Shutdown. Same as SHDN pin operation except inverse logic (only affects

selected channel)

O2, O1 = Output Logic Pin Latched Values, Default Logic 0

D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits

SCL

SDA

START BY

MASTER

1

9

1

9

1

9

0

10

1

1 AD1 AD0 R/W

A/B RS SD O1 O2 X X X

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 1

SLAVE ADDRESS BYTE

ACK. BY

AD5280/AD5282

FRAME 2

INSTRUCTION BYTE

ACK. BY

AD5280/AD5282

FRAME 3

DATA BYTE

ACK. BY

AD5280/AD5282

STOP BY

MASTER

Figure 2. Writing to the RDAC Register

1

9

1

9

SCL

SDA

START BY

MASTER

0

10

1

1 AD1 AD0 R/W

D7 D6 D5 D4 D3 D2 D1 D0 A

FRAME 1

SLAVE ADDRESS BYTE

ACK. BY

AD5280/AD5282

NO ACK. BY

MASTER

FRAME 2

DATA BYTE FROM PREVIOUSLY SELECTED

STOP BY

MASTER

RDAC REGISTER IN WRITE MODE

Figure 3. Reading Data from a Previously Selected RDAC Register in Write Mode

–10–

REV. 0

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