AD5338RBRUZ-RL7(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5338RBRUZ-RL7
(Rev.:Rev0)

Dual, 10-Bit nanoDAC with 2 ppm/°C Reference, I2C Interface

Analog Devices 

Data Sheet

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5338R is a dual, 10-bit, serial input, voltage output DAC

with an internal reference. The part operates from supply voltages

of 2.7 V to 5.5 V. Data is written to the AD5338R in a 24-bit word

format via a 2-wire serial interface. The AD5338R incorporates a

power-on reset circuit to ensure that the DAC output powers up to

a known output state. The device also has a software power-down

mode that reduces the typical current consumption to 4 µA.

TRANSFER FUNCTION

The internal reference is on by default. To use an external reference,

only a nonreference option is available. Because the input coding

to the DAC is straight binary, the ideal output voltage when using

an external reference is given by

VOUT

= VREF

× Gain

D

 2N





where:

Gain is the gain of the output amplifier and is set to 1 by default.

This can be set to ×1 or ×2 using the gain select pin. When this

pin is tied to GND, both DAC outputs have a span from 0 V to

VREF. If this pin is tied to VLOGIC, both DACs output a span of 0 V

to 2 × VREF.

D is the decimal equivalent of the binary code that is loaded to the

DAC register as 0 to 1,023 for the 10-bit device.

N is the DAC resolution.

DAC ARCHITECTURE

The DAC architecture consists of a string DAC followed by an

output amplifier. Figure 41 shows a block diagram of the DAC

architecture.

VREF

2.5V

REF

INPUT

REGISTER

DAC

REGISTER

REF (+)

RESISTOR

STRING

REF (–)

VOUTX

GND

GAIN

(GAIN = 1 OR 2)

Figure 41. Single DAC Channel Architecture Block Diagram

AD5338R

The resistor string structure is shown in Figure 42. It is a string

of resistors, each of Value R. The code loaded to the DAC register

determines the node on the string where the voltage is to be

tapped off and fed into the output amplifier. The voltage is tapped

off by closing one of the switches connecting the string to the

amplifier. Because it is a string of resistors, it is guaranteed

monotonic.

VREF

R

R

R

TO OUTPUT

AMPLIFIER

R

R

Figure 42. Resistor String Structure

Internal Reference

The AD5338R on-chip reference is on at power-up but can

be disabled via a write to a control register. See the Internal

Reference Setup section for details.

The AD5338R has a 2.5 V, 2 ppm/°C reference, giving a full-scale

output of 2.5 V or 5 V depending on the state of the GAIN pin.

The internal reference associated with the device is available at

the VREF pin. This buffered reference is capable of driving external

loads of up to 10 mA.

Output Amplifiers

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to VDD. The actual

range depends on the value of VREF, the GAIN pin, the offset error,

and the gain error. The GAIN pin selects the gain of the output.

• If GAIN is tied to GND, both outputs have a gain of 1, and

the output range is 0 V to VREF.

• If GAIN is tied to VLOGIC, both outputs have a gain of 2, and

the output range is 0 V to 2 × VREF.

These amplifiers are capable of driving a load of 1 kΩ in parallel

with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale

settling time of 5 µs.

Rev. 0 | Page 17 of 28

Share Link: