AD5663RBCPZ-3R2(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5663RBCPZ-3R2
(Rev.:RevA)

Dual 12-/14-/16-Bit nanoDAC® with 5 ppm/°C On-Chip Reference

Analog Devices 

AD5623R/AD5643R/AD5663R

At this stage, the SYNC line can be kept low or be brought high.

In either case, it must be brought high for a minimum of 15 ns

before the next write sequence, so that a falling edge of SYNC

can initiate the next write sequence.

Because the SYNC buffer draws more current when VIN = 2 V

than it does when VIN = 0.8 V, SYNC should be idled low between

write sequences for even lower power operation. As mentioned

previously, it must, however, be brought high again just before

the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (see Figure 52). The first

two bits are don’t cares. The next three are Command Bit C2 to

Command Bit C0 (see Table 8), followed by the 3-bit DAC

Address A2 to DAC Address A0 (see Table 9), and, finally, the

16-, 14-, and 12-bit data-word.

The data-word comprises the 16-, 14-, and 12-bit input codes,

followed by zero, two, or four don’t care bits, for the AD5663R,

AD5643R, and AD5623R, respectively (see Figure 51, Figure 52,

and Figure 53). The data bits are transferred to the DAC register

on the 24th falling edge of SCLK.

Table 8. Command Definition

C2 C1 C0 Command

0 0 0 Write to Input Register n

0 0 1 Update DAC Register n

0 1 0 Write to Input Register n, update all

(software LDAC)

0 1 1 Write to and update DAC Channel n

1 0 0 Power down DAC (power up)

1 0 1 Reset

1 1 0 LDAC register setup

1 1 1 Internal reference setup (on/off )

Table 9. Address Command

A2

A1

A0

0

0

0

0

0

1

0

1

0

0

1

1

1

1

1

ADDRESS (n)

DAC A

DAC B

Reserved

Reserved

All DACs

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 24 falling edges of SCLK, and the DAC is updated on the

24th falling edge. However, if SYNC is brought high before the

24th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset, and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see Figure 54).

DB23 (MSB)

DB0 (LSB)

X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

COMMAND BITS ADDRESS BITS

DATA BITS

Figure 51. AD5663R Input Shift Register Contents

DB23 (MSB)

DB0 (LSB)

X X C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

COMMAND BITS ADDRESS BITS

DATA BITS

Figure 52. AD5643R Input Shift Register Contents

DB23 (MSB)

X X C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X

COMMAND BITS ADDRESS BITS

DATA BITS

Figure 53. AD5623R Input Shift Register Contents

DB0 (LSB)

XXX

SCLK

SYNC

DIN

DB23

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24TH FALLING EDGE

DB23

DB0

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 24TH FALLING EDGE

Figure 54. SYNC Interrupt Facility

Rev. A | Page 21 of 28

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