EVAL-AD7142EB View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
EVAL-AD7142EB
Analog Devices
EVAL-AD7142EB Datasheet PDF : 68 Pages
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AD7142
16-BIT COMMAND WORD
ENABLE WORD
R/W
STARTING REGISTER ADDRESS
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
SDI
CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW D15 D14
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
D1 D0 D15 D14
D1 D0 D15
SCLK
1
2
3
4
5
6
7
8
9 10
11 12 13 14 15 16 17 18
31 32 33 34
47 48 49
CS
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
Figure 45. Sequential Register Write SPI Timing
16-BIT COMMAND WORD
SDI
SCLK
CS
SDO
ENABLE WORD
R/W
REGISTER ADDRESS
CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
X
X
X
t2
t4
t5
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
t1
t3
t6
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D13
X
X
X
30 31 32
t8
t7
D2 D1 D0 XXX
16-BIT READBACK DATA
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE SDO PIN.
4. X DENOTES DON’T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
Figure 46. Single Register Readback SPI Timing
Reading Data
A read transaction begins when the master writes the command
word to the AD7142 with the read/write bit set to 1. The master
then supplies 16 clock pulses per data-word to be read, and the
AD7142 clocks out data from the addressed register on the SDO
line. The first data-word is clocked out on the first falling edge
of SCLK following the command word, as shown in Figure 46.
The AD7142 continues to clock out data on the SDO line
provided the master continues to supply the clock signal on
SCLK. The read transaction finishes when the master takes
CS high. If the AD7142 address pointer reaches its maximum
value, then the AD7142 repeatedly clocks out data from the
addressed register. The address pointer does not wrap around.
Rev. 0 | Page 31 of 68
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