AD7879ACPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7879ACPZ-RL Datasheet PDF : 40 Pages
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AD7879/AD7889
Data Sheet
CONTROL REGISTER 2
Table 22. First Conversion Delay Selection
Control Register 2 (Address 0x02) contains the ADC
power management bits, the GPIO settings, the SER/DFR bit
(to choose the single-ended or differential method of touch
screen measurement), the averaging and median filter settings,
a bit that allows resetting of the device, and the first conversion
delay bits. Its power-on default value is 0x4040. See the Detailed
Register Descriptions section for more information about the
control registers.
For information about the averaging and median filter settings,
see the Median and Averaging Filters section. For information
about the GPIO settings, see the GPIO section.
FCD[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Delay
128 μs
256 μs
384 μs
512 μs
640 μs
768 μs
896 μs
1.024 ms
1.152 ms
1.280 ms
1.536 ms
First Conversion Delay (Control Register 2, Bits[3:0])
1011
1.792 ms
The first conversion delay (FCD) bits in Control Register 2
program a delay from 128 μs (default) up to 4.096 ms before
the first conversion to allow the ADC time to power up. This
delay also occurs before conversion of the X and Y coordinate
1100
1101
1110
1111
2.048 ms
2.560 ms
3.584 ms
4.096 ms
channels to allow extra time for screen settling, and after the
last conversion in a sequence to precharge PENIRQ.
15
0
PM1
PM0
GPIO
EN
GPIO
DAT
GPIO
DIR
GPIO
POL
SER/
DFR
AVG1 AVG0 MED1 MED0
SW/
RST
FCD3 FCD2 FCD1 FCD0
Figure 31. Control Register 2
Rev. D | Page 28 of 40
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