AD8142ACPZ-RL(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD8142ACPZ-RL Datasheet PDF : 24 Pages
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AD8141/AD8142
+IN R
–IN R
VSYNC
AD8142
2kΩ
1kΩ
+
VOCM R
–
1kΩ
2kΩ
–OUT R
+OUT R
HSYNC
SYNC LEVEL
+IN G
–IN G
2kΩ
1kΩ
+
VOCM G
×2
–
1kΩ
2kΩ
–OUT G
+OUT G
+IN B
–IN B
DIS
2kΩ
1kΩ
+
VOCM B
–
1kΩ
2kΩ
–OUT B
+OUT B
VOCM WEIGHTING EQUATIONS ON +5V SUPPLY:
RED
VOCM
=
K
2
(VSYNC
–
HSYNC)
+
1.5V
GREEN
VOCM
=
K
2
(–2VSYNC)
+
1.5V
BLUE
VOCM =
K
2
(VSYNC
+
HSYNC)
+
1.5V
Figure 47. AD8142 Conceptual Sync-On-Common-Mode Encoding Scheme
The transmitted common-mode sync signal magnitudes are
scaled by applying a dc voltage to the SYNC LEVEL input,
referenced to the negative supply. The difference between the
voltage applied to the SYNC LEVEL input and the negative supply
sets the peak deviation of the encoded sync signals about the
midsupply common-mode voltage. For example, with the SYNC
LEVEL input set at VS− + 500 mV, the deviation of the encoded
sync pulses about the nominal midsupply common-mode voltage
is nominally ±500 mV. The equations in Figure 47 describe how
the VSYNC and HSYNC signals are encoded on each color’s midsupply
common-mode signal. In these equations, the weights of the VSYNC
and HSYNC signals are ±1 (that is, +1 for high, −1 for low), and the
constant, K, is equal to the peak deviation of the encoded sync
signals.
Figure 48 shows how the sync signals appear on each common-
mode voltage in a single 5 V supply application when the voltage
applied to the SYNC LEVEL input is set to VS− + 500 mV.
Although the typical setting for the SYNC LEVEL voltage is
500 mV above the negative supply, it can be increased, if
necessary, in extremely noisy environments. Increasing the
SYNC LEVEL voltage too much has the potential to produce
excessive EMI.
2.25
2.00
GCM
17.5
SYNC LEVEL = 0.5V
1.75
RCM
1.50
BCM
12.5
1.25
7.5
1.00
0.75
0.50
HSYNC
VSYNC
2.5
0.25
0
–2.5
0 40 80 120 160 200 240 280 320 360 400
TIME (ns)
Figure 48. AD8142 Sync-On-Common-Mode Signals in Single 5 V Application
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
When designing with the AD8141 and AD8142, adhere to
standard high speed printed circuit board (PCB) layout practices.
A solid ground plane is recommended and good wideband power
supply decoupling networks should be placed as close as possible
to the supply pins. Small surface-mount ceramic capacitors are
recommended for these networks, and tantalum capacitors are
recommended for bulk supply decoupling.
AMPLIFIER-TO-AMPLIFIER ISOLATION
The least amount of isolation between the three AD8142 amplifiers
exists between the green and red channels (Amplifier A and
Amplifier B for the AD8141). This is, therefore, viewed as the
worst-case isolation, which is reflected in Table 1 and the
Theory of Operation section.
EXPOSED PADDLE (EPAD)
The 24-lead LFCSP package has an exposed paddle on the
underside of its body. To achieve the specified thermal resistance, it
must have a good thermal connection to one of the PCB planes.
The exposed paddle must be soldered to a pad on top of the board
that is connected with several thermal vias to a ground plane.
Rev. 0 | Page 22 of 24
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