AD8148ACPZ-RL(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD8148ACPZ-RL Datasheet PDF : 24 Pages
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AD8147/AD8148
+IN R
–IN R
VSYNC
500Ω
500Ω
1kΩ
VOCM R
1kΩ
–OUT R
+OUT R
HSYNC
SYNC LEVEL
+IN G
–IN G
1kΩ
500Ω
×2
500Ω
VOCM G
1kΩ
–OUT G
+OUT G
1kΩ
+IN B
–IN B
OPD
500Ω
500Ω
VOCM B
1kΩ
–OUT B
+OUT B
VOCM WEIGHTING EQUATIONS:
RED VOCM = K2 (VSYNC – HSYNC) + VMIDSUPPLY
GREEN VOCM = K2 (–2VSYNC) + VMIDSUPPLY
BLUE VOCM = K2 (VSYNC + HSYNC) + VMIDSUPPLY
Figure 30. AD8147/AD8148 Sync-On Common-Mode Encoding Scheme
AD8146/AD8147/AD8148
3.1
3.0
G
2.9
2.8
2.7
2.6
2.5
R
2.4
2.3
2.2
2.1
B
2.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
HSYNC
1.5
VSYNC
1.0
0.5
0
0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07
TIME (µs)
Figure 31. AD8147 Sync-On Common-Mode Signals in Single 5 V Application
The transmitted common-mode sync signal magnitudes are
scaled by applying a dc voltage to the SYNC LEVEL input,
referenced to GND. The difference between the voltage applied
to the SYNC LEVEL input and GND sets the peak deviation of
the encoded sync signals about the midsupply, common-mode
voltage. For example, with the SYNC LEVEL input set at 500 mV,
the deviation of the encoded sync pulses about the nominal
midsupply, common-mode voltage is typically ±500 mV. The
equations in Figure 30 describe how the VSYNC and HSYNC signals
are encoded on each color’s midsupply common-mode signal.
In these equations, the weights of the VSYNC and HSYNC signals
are ±1 (+1 for high and −1 for low), and the constant K is equal
to the peak deviation of the encoded sync signals.
Figure 31 shows how the sync signals appear on each common-
mode voltage in a single 5 V supply application when the voltage
applied to the SYNC LEVEL input is 500 mV, which is the
typical setting for most applications.
Rev. 0 | Page 17 of 24
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