AD8202
SPECIFICATIONS
SINGLE SUPPLY
TA = operating temperature range, VS = 5 V, unless otherwise noted.
Table 1.
Parameter
SYSTEM GAIN
Initial
Error
vs. Temperature
VOLTAGE OFFSET
Input Offset (RTI)
vs. Temperature
INPUT
Input Impedance
Differential
Common Mode
CMV
CMRR1
PREAMPLIFIER
Gain
Gain Error
Output Voltage Range
Output Resistance
OUTPUT BUFFER
Gain
Gain Error
Output Voltage Range
Input Bias Current
Output Resistance
DYNAMIC RESPONSE
System Bandwidth
Slew Rate
NOISE
0.1 Hz to 10 Hz
Spectral Density, 1 kHz (RTI)
POWER SUPPLY
Operating Range
Quiescent Current vs.
Temperature
PSRR
TEMPERATURE RANGE
For Specified Performance
Conditions
AD8202 SOIC
Min Typ Max
20
0.02 ≤ VOUT ≤ 4.8 V dc @ 25°C −0.3
+0.3
1 20
VCM = 0.15 V; 25°C
−40°C to +125°C
−40°C to +150°C
−1
+1
−10 +0.3 +10
Continuous
VCM = −8 V to +28 V
f = dc
f = 1 kHz
f = 10 kHz2
260 325 390
135 170 205
−8
+28
82
82
80
10
−0.3
+0.3
0.02
4.8
97 100 103
0.02 ≤ VOUT ≤ 4.8 V dc
2
−0.3
+0.3
0.02
4.8
40
2
VIN = 0.1 V p-p; VOUT = 2.0 V p-p 30 50
VIN = 0.2 V dc; VOUT = 4 V step
0.28
10
275
VO = 0.1 V dc
VS = 3.5 V to 12 V
3.5
12
0.25 1.0
75 83
−40
+125
AD8202 MSOP
Min Typ Max
20
1 25
−2
+2
−20 +2 +20
260 325 390
135 170 205
−8
+28
82
82
80
10
−0.3
+0.3
0.02
4.8
97 100 103
2
−0.3
+0.3
0.02
4.8
40
2
30 50
0.28
10
275
3.5
12
0.25 1.0
75 83
−40
+125
AD8202 Die
Min Typ Max
20
−0.3
+0.3
1 30
−1
+1
−10 +0.3 +10
−15 +5 +15
260 325 390
135 170 205
−8
+28
82
82
80
10
−0.3
+0.3
0.02
4.8
97 100 103
2
−0.3
+0.3
0.02
4.8
40
2
30 50
0.28
10
275
3.5
12
0.25 1.0
75 83
−40
+150
Unit
V/V
%
ppm/°C
mV
μV/°C
μV/°C
kΩ
kΩ
V
dB
dB
dB
V/V
%
V
kΩ
V/V
%
V
nA
Ω
kHz
V/μs
μV p-p
nV/√Hz
V
mA
dB
°C
1 Source imbalance <2 Ω.
2 The AD8202 preamplifier exceeds 80 dB CMRR at 10 kHz. However, because the signal is available only by way of a 100 kΩ resistor, even the small amount of pin-to-
pin capacitance between Pin 1, Pin 8 and Pin 3, Pin 4 might couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of
pin-to-pin coupling can be neglected in all applications by using filter capacitors at Node 3.
Rev. D | Page 3 of 20