AD8364ACPZ-WP(RevB) View Datasheet(PDF) - Analog Devices
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AD8364ACPZ-WP Datasheet PDF : 44 Pages
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AD8364
GENERAL DESCRIPTION AND THEORY
The AD8364 is a dual-channel, 2.7 GHz, true rms responding
detector with 60 dB measurement range. It incorporates two
AD8362 channels with shared reference circuitry (See the
AD8362 datasheet for more information). Multiple enhancements
have been made to the AD8362 cores to improve measurement
accuracy. Log-conformance peak-to-peak ripple has been reduced
to <±0.2 dB over the entire dynamic range. Temperature stability
of the rms output measurements provides <±0.5 dB error over
the specified temperature range of −40°C to 85°C through
proprietary techniques. The use of well-matched channels offers
extremely temperature-stable difference outputs, OUTP and
OUTN. Given well-matched channels through IC integration,
the rms measurement outputs, OUTA and OUTB, drift in the
same manner. With OUTP shorted to FBKA, the function at
OUTP is
OUTP = OUTA – OUTB + VLVL
(1)
When OUTN is shorted to FBKB, the function at OUTN is
OUTN = OUTB – OUTA + VLVL
(2)
OUTP and OUTN are insensitive to the common drift due to
the difference cancellation of OUTA and OUTB.
The AD8364 is a fully calibrated rms-to-dc converter capable of
operating on signals of a few hertz to 2.7 GHz or more. Unlike
logarithmic amplifiers, the AD8364 response is waveform
independent. The device accurately measures waveforms that
have a high peak-to-rms ratio (crest factor). Figure 50 shows a
block diagram.
A single channel of the AD8364 consists of a high performance
AGC loop. As shown in Figure 51, the AGC loop comprises
a wide bandwidth variable gain amplifier (VGA), square law
detectors, an amplitude target circuit, and an output driver. For
a more detailed description of the functional blocks, see the
AD8362 data sheet.
Data Sheet
VPSA 25
INHA 26
INLA 27
PWDN 28
COMR 29
INLB 30
INHB 31
VPSB 32
24 23 22 21 20 19 18 17
TEMP
VGA
CONTROL
CHANNEL A
TruPwr™
ISIG2
ITGT2
OUTA
OUTB
CHANNEL B
TruPwr™
ISIG2
ITGT2
VGA
BIAS CONTROL
1
2
3
4
5
6
78
16 VSTA
15 OUTA
14 FBKA
13 OUTP
12 OUTN
11 FBKB
10 OUTB
9 VSTB
Figure 50. Block Diagram
VIN
INH[A, B]
INL[A, B]
VGA
x2
VSIG
OFFSET
CHP[A, B] NULLING
GSET
VST[A, B]
VST[A, B]
SETPOINT
INTERFACE
CLP [A, B]
VREF
VREF
2.5V
BAND GAP
REFERENCE
CLPF
EXTERNAL
x2
TEMPERATURE
COMPENSATION
VREF × 0.03
OUTPUT
BUFFER
CF
ADJ[A, B]
OUT[A, B]
ACOM
Figure 51. Single-Channel Details
Rev. B | Page 18 of 44
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