AD8375ACPZ-WP(Rev0) View Datasheet(PDF) - Analog Devices
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Description
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AD8375ACPZ-WP Datasheet PDF : 24 Pages
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LAYOUT CONSIDERATIONS
There are two output pins for each polarity, and they are
oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
A good practice is to avoid any ground or power plane under
this routing region and under the chokes to minimize the
parasitic capacitance.
CHARACTERIZATION TEST CIRCUITS
Differential-to-Differential Characterization
The S-parameter characterization for the AD8375 was
performed using a dedicated differential input to differential
output characterization board. Figure 44 shows the layout of
characterization board. The board was designed for optimum
impedance matching into a 75 Ω system. Because both the
input and output impedances of the AD8375 are 150 Ω
differentially, 75 Ω impedance runs were used to match 75 Ω
network analyzer port impedances. On-board 1 μH inductors
were used for output biasing, and the output board traces were
designed for minimum capacitance.
+5V
L1 L2
1µH 1µH
0.1µF
75Ω
0.1µF
75Ω
AC
75Ω TRACES
AD8375
75Ω TRACES
AC
75Ω
0.1µF
5
75Ω
0.1µF
A0 TO A4
Figure 42. Test Circuit for S-Parameters on Dedicated 75 Ω
Differential-to-Differential Board
AD8375
+9V
0.1µF
TC3-1T
96Ω 96Ω
0.1µF 330Ω 25Ω
50Ω
T1
AD8375
50Ω
AC
0.1µF
5
0.1µF 330Ω 25Ω
A0 TO A4
Figure 43. Test Circuit for Time Domain Measurements
Figure 44. Differential-to-Differential Characterization Board
Circuit Side Layout
+5V
C1
TC3-1T 0.1µF
L1 L2
1µH
1µH
C3
0.1µF
R1
62Ω
R4
25Ω ETC1-1-13
50Ω
T1
AC
AD8375
C2
0.1µF 5
PAD LOSS = 11dB
C4 R2
R3
0.1µF 62Ω 25Ω
T2 50Ω
A0 TO A4
Figure 45. Test Circuit for Distortion, Gain, and Noise
Rev. 0 | Page 17 of 24
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