AD8380JS View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD8380JS
Analog Devices
AD8380JS Datasheet PDF : 16 Pages
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AD8380–SPECIFICATIONS (@ 25؇C, AVCC = 15 V, DVCC = 3.3 V, TMIN = 0؇C, TMAX = 85؇C, unless
otherwise noted)
Model
VIDEO DC PERFORMANCE1
VDE
VCME
Scale Factor Error
Offset Error
REFERENCE INPUTS
VMID Range2
VMID Bias Current
VFS Range
VREFHI
VREFLO
VREFHI Input Resistance
VREFLO Bias Current
VREFHI Input Current3
RESOLUTION
Coding
DIGITAL INPUT CHARACTERISTICS
Input Data Update Rate
Clock to Data Setup Times: t1
Clock to STSQ Setup Times: t3
Clock to XFR Setup Times: t5
Maximum CLK Rise and Fall Time, t7
Clock to A[0:2] Hold Times: t9
Clock to Data Hold Times: t2
Clock to STSQ Hold Times: t4
Clock to XFR Hold Times: t6
Clock to A[0:2] Setup Times: t8
CIN
IIN
VIH
VIL
VTH
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
CLK to VID Delay4
Output Current
VIDEO OUTPUT DYNAMIC PERFORMANCE
Data Switching Slew Rate
Invert Switching Slew Rate
Data Switching Settling Time to 1%5
Data Switching Settling Time to 0.25%
Invert Switching Settling Time to 1%5
Invert Switching Settling Time to 0.25%
CLK Feedthrough6
All-Hostile Crosstalk7
Amplitude
Glitch Duration
POWER SUPPLY
Supply Rejection (VDE)
DVCC, Operating Range
DVCC, Quiescent Current
AVCC, Operating Range
Total AVCC Quiescent Current
STBY AVCC Current
STBY DVCC Current
OPERATING TEMPERATURE RANGE
Conditions
TMIN to TMAX
DAC Code = 450 to 800
DAC Code = 450 to 800
DAC Code = 0 to 1023
DAC Code = 0 to 1023
VFS = 2 × (VREFHI–VREFLO)
to VREFLO
VFS = 5 V
Binary
Threshold Voltage
AVCC – VOH, VOL – AVEE
50% of VIDx
TMIN to TMAX, VO = 5 V Step,
CL = 150 pF, RS = 25 Ω
+VS = 15 V ± 1 V
STBY = H
STBY = H
Min
–7.5
–3.5
–0.25
–7
6
1
VREFLO +0.5
VMID – 0.5
10
1
1
1
4
4
4
4
4
1
2.0
13.5
30
3
9
0
Typ
Max
Unit
+1
+7.5
mV
+0.5
+3.5
mV
+0.25
%
+1
+7
mV
7
7.5
V
3
µA
5
6
V
AVCC – 2.5 AVCC
V
VREFHI – 2.5 VREFHI – 0.5 V
3.3
kΩ
0.2
µA
750
µA
Bits
75
3
0.6
0.8
1.4
Ms/s
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
µA
V
V
V
1.1
1.3
V
15.5
17.5
ns
mA
270
625
26
32
35
65
30
40
85
100
2
5
95
40
1
5.5
22
35
24
33
44
0.5
5
0.1
5
85
V/µs
V/µs
ns
ns
ns
ns
mV p-p
mV p-p
ns
mV/V
V
mA
V
mA
mA
mA
°C
NOTES
1For definitions of VDE and VCME, see the Transfer Function section. Scale factor error is expressed as percentage of VFS.
2See Figure 1 for valid ranges of VMID.
3VREFHI Input Current = (VREFHI – VREFLO)/(VREFHI Input Resistance) = 2.5 V/3.3 kΩ.
4Delay time from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.
5For best settling time results, use minimum series output resistance, RS of 25 Ω.
6An output channel is selected, and glitch is monitored as CLK is driven. STSQ and XFR are set to logic low.
7Input data is loaded such that any five output channels change by VFS (i.e., 5 V), and the sixth unselected channel is monitored. Measurement is made for both states of INV.
Specifications subject to change without notice.
–2–
REV. B
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