AD9548(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9548 Datasheet PDF : 112 Pages
| |||
AD9548
Table 67. Distribution Synchronization
Address
Bits
Bit Name
0402
[7:6]
Unused
[5:4]
Sync source
[3]
OUT3 sync mask
[2]
OUT2 sync mask
[1]
OUT1 sync mask
[0]
OUT0 sync mask
Table 68. Automatic Synchronization
Address
Bits
Bit Name
0403
[7:2]
Unused
[1:0]
Automatic sync mode
Table 69. Distribution Channel Modes
Address
Bits
Bit Name
0404
[7:6]
Unused
[5]
OUT0 CMOS phase
invert
[4]
OUT0 polarity invert
[3]
OUT0 drive strength
[2:0]
OUT0 mode
Description
Select the sync source for the clock distribution output channels.
00 (default) = direct.
01 = active reference.
10 = DPLL feedback edge.
11 = reserved.
Mask the synchronous reset to the OUT3 divider.
0 (default) = unmasked
1 = masked.
Mask the synchronous reset to the OUT2 divider.
0 (default) = unmasked.
1 = masked.
Mask the synchronous reset to the OUT1 divider.
0 (default) = unmasked.
1 = masked.
Mask the synchronous reset to the OUT0 divider.
0 (default) = unmasked.
1 = masked.
Description
Autosync mode
00 (default) = disabled
01 = sync on DPLL frequency lock
10 = sync on DPLL phase lock
11 = reserved
Description
When the output mode is CMOS, the bit inverts the relative phase between the two
CMOS output pins. Otherwise, this bit is nonfunctional.
0 (default) = not inverted.
1 = inverted.
Invert the polarity of OUT0.
0 (default) = not inverted.
1 = inverted.
OUT0 output drive capability control.
0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.
1 = CMOS: normal drive strength; LVDS: 7 mA nominal.
OUT0 operating mode select.
000 = CMOS (both pins)
001 = CMOS (positive pin), tristate (negative pin).
010 = tristate (positive pin), CMOS (negative pin).
011 (default) = tristate (both pins).
100 = LVDS.
101 = LVPECL.
110 = reserved.
111 = reserved.
Rev. 0 | Page 78 of 112
Share Link: 