AD9572(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9572
(Rev.:Rev0)

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

Analog Devices 

AD9572

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

PLL Characteristics ...................................................................... 3

LVDS Clock Output Jitter............................................................ 4

LVPECL Clock Output Jitter....................................................... 5

CMOS Clock Output Jitter .......................................................... 5

Reference Input............................................................................. 5

Clock Outputs ............................................................................... 6

Timing Characteristics ................................................................ 6

Control Pins .................................................................................. 7

Power.............................................................................................. 7

Crystal Oscillator.......................................................................... 7

Timing Diagrams.............................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

REVISION HISTORY

7/09—Revision 0: Initial Version

ESD Caution...................................................................................9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 14

Outputs ........................................................................................ 14

Phase Frequency Detector (PFD) and Charge Pump............ 15

Power Supply............................................................................... 15

CMOS Clock Distribution ........................................................ 15

LVPECL Clock Distribution ..................................................... 16

LVDS Clock Distribution .......................................................... 16

Reference Input........................................................................... 16

Power and Grounding Considerations and Power Supply

Rejection...................................................................................... 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. 0 | Page 2 of 20

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