AD9736BBCRL(RevB) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9736BBCRL Datasheet PDF : 72 Pages
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AD9734/AD9735/AD9736
The LVDS and sync controllers are independently operated in
three modes via SPI port Reg. 6 and Reg. 8:
• Manual mode
• Surveillance mode
• Auto mode
In manual mode, all of the timing measurements and updates
are externally controlled via the SPI.
In surveillance mode, each controller takes measurements and
calculates a new optimal value continuously. The result of the
measurement is passed through an averaging filter before
evaluating the results for increased noise immunity. The filtered
result is compared to a threshold value set via Reg. 6 and Reg. 8
of the SPI port. If the error is greater than the threshold, an
interrupt is triggered and the controller stops.
Reg. 1 of the SPI port controls the interrupts with Bit 3 and Bit 2
enabling the respective interrupts and Bit 7 and Bit 6 indicating
the respective controller interrupt. If an interrupt is enabled, it
also activates the AD973x IRQ pin. To clear an interrupt, the
interrupt enable bit of the respective controller must be set to 0
for at least 1 controller clock cycle (controller clock <10 MHz).
Auto mode is almost identical to surveillance mode. Instead
of triggering an interrupt and stopping the controller, the
controller automatically updates its settings to the newly
calculated optimal value and continues to run.
LVDS SAMPLE LOGIC
A simplified diagram of the AD973x LVDS data sampling
engine is shown in Figure 78 and the timing diagram is shown
in Figure 79.
The incoming LVDS data is latched by the data sampling signal
(DSS), which is derived from DATACLK_IN. The LVDS
controller delays DATACLK_IN to create the data sampling
signal (DSS), which is adjusted to sample the LVDS data in the
center of the valid data window. The skew between the
DATACLK_IN and the LVDS data bits (DB<13:0>) must be
minimal for proper operation. Therefore, it is recommended
that the DATACLK_IN be generated in the same manner as the
LVDS data bits (DB<13:0>) with the same driver and data lines
(that is, it should just be another LVDS data bit running a
constant 01010101… sequence, as shown in Figure 96).
If the DATACLK_IN signal is stopped, the DACCLK continues
to generate an output signal based on the last two values
clocked into the registers that drive D1 and D2, as shown in
Figure 78. If these two registers are not equal, a large output at a
frequency of one-half fDAC can be generated at the DAC output.
Data Sheet
DB<13:0>
LVDS
RX
DATA SAMPLING
SIGNAL
DBU
FF
D1
DBL
FF
D2
DATACLK_IN
LVDS
RX
SD<3:0>
SAMPLE DELAY
DELAYED
CLOCK
SIGNAL
MSD<3:0>
DELAY
FF
CHECK
MHD<3:0>
DELAY
CLOCK
SAMPLING
SIGNAL
Figure 78. Internal LVDS Data Sampling Logic
CLK TO DB SKEW
SAMPLE
DELAY
PROP DELAY
TO LATCH
PROP DELAY
TO LATCH
DB13:0
DATACLK_IN
DATA SAMPLING
SIGNAL (DSS)
D1
D2
Figure 79. Internal LVDS Data Sampling Logic Timing
LVDS SAMPLE LOGIC CALIBRATION
The internal DSS delay must be calibrated to optimize the data
sample timing. Once calibrated, the AD973x generates an IRQ
or automatically corrects its timing if temperature or voltage
variations change the timing too much. This calibration is done
using the delayed clock sampling signal (CSS) to sample the
delayed clock signal (DCS). The LVDS sampling logic finds the
edges of the DATACLK_IN signal and, from this measurement,
the center of the valid data window is located.
The internal delay line that derives the delayed DSS from
DATACLK_IN is controlled by SD3:0 (Reg. 5, Bits 7:4), while
the DCS is controlled by MSD3:0 (Reg. 4, Bits 7:4), and the CSS
is controlled by MHD3:0 (Reg. 4, Bits 3:0).
DATACLK_IN transitions must be time aligned with the LVDS
data (DB<13:0>) transitions. This allows the CSS, derived from
the DATACLK_IN, to find the valid data window of DB<13:0>
by locating the DATACLK_IN edges. The latching (rising) edge
of CSS is initially placed using Bits SD<3:0> and can then be
shifted to the left using MSD<3:0> and to the right using
MHD<3:0>. When CSS samples the DCS and the result is 1
(which can be read back via the check bit at Reg. 5, Bit 0), the
sampling occurs in the correct data cycle.
Rev. B | Page 40 of 72
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