AD9747-EBZ View Datasheet(PDF) - Analog Devices
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AD9747-EBZ Datasheet PDF : 28 Pages
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internally by the serial port controller by decrementing from
the specified address. For LSB-first format, the specified address
is a beginning address or the least significant address in the
current cycle. Remaining register addresses for multiple byte
data transfers are generated internally by the serial port
controller by incrementing from the specified address.
MSB/LSB TRANSFERS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register 0x00, Bit 6.
The default is Logic 0, which is MSB-first format.
When using MSB-first format (LSBFIRST = 0), the instruction
and data bit must be written from MSB to LSB. Multibyte data
transfers in MSB-first format start with an instruction byte that
includes the register address of the most significant data byte.
Subsequent data bytes are loaded into sequentially lower
address locations. In MSB-first mode, the serial port internal
address generator decrements for each byte of the multibyte
data transfer.
When using LSB-first format (LSBFIRST = 1), the instruction
and data bit must be written from LSB to MSB. Multibyte data
transfers in LSB-first format start with an instruction byte that
includes the register address of the least significant data byte.
Subsequent data bytes are loaded into sequentially higher
address locations. In LSB-first mode, the serial port internal
address generator increments for each byte of the multibyte
data transfer.
Use of a single-byte transfer when changing the serial port data
format is recommended to prevent unexpected device behavior.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
Chip Select Bar (CSB)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communication lines. CSB must stay low during the entire
communication cycle. Incomplete data transfers are aborted
anytime the CSB pin goes high. SDO and SDIO pins go to a
high impedance state when this input is high.
Serial Clock (SCLK)
The serial clock pin is used to synchronize data to and from the
device and to run the internal state machines. The maximum
frequency of SCLK is 40 MHz. All data input is registered on
the rising edge of SCLK. All data is driven out on the falling
edge of SCLK.
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However,
SDIO can also function as a bidirectional data output line.
AD9741/AD9743/AD9745/AD9746/AD9747
The configuration of this pin is controlled by Register 0x00,
Bit 7. The default is Logic 0, which configures the SDIO pin
as unidirectional.
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. The configuration of this
pin is controlled by Register 0x00, Bit 7. If this bit is set to a
Logic 1, the SDO pin does not output data and is set to a high
impedance state.
CSB
SCLK
SDIO
SDO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6N D5N
D30 D20 D10 D00
D7 D6N D5N
D30 D20 D10 D00
Figure 23. Serial Register Interface—MSB First
CSB
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
SDO
A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20
D4N D5N D6N D7N
D00 D10 D20
D4N D5N D6N D7N
Figure 24. Serial Register Interface Timing—LSB First
CSB
SCLK
SDIO
tS
fSCLK–1
tPWH
tPWL
tDS
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
Figure 25. Timing Diagram for SPI Register Write
CSB
SCLK
SDIO
SDO
tDV
DATA BIT N
DATA BIT N – 1
Figure 26. Timing Diagram for SPI Register Read
Rev. 0 | Page 19 of 28
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