AD9753-EB(Rev0) View Datasheet(PDF) - Analog Devices
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AD9753-EB Datasheet PDF : 26 Pages
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AD9753
REFERENCE CONTROL AMPLIFIER
The AD9753 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a voltage-to-current con-
verter as shown in Figure 4, so that its current output, IREF, is
determined by the ratio of VREFIO and an external resistor, RSET,
as stated in Equation 4. IREF is applied to the segmented current
sources with the proper scaling factor to set IOUTFS as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between
62.5 µA and 625 µA. The wide adjustment span of IOUTFS provides
several application benefits. The first benefit relates directly to
the power dissipation of the AD9753, which is proportional to
IOUTFS (refer to the Power Dissipation section). The second
benefit relates to the 20 dB adjustment, which is useful for sys-
tem gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency, small
signal multiplying applications.
PLL CLOCK MULTIPLIER OPERATION
The Phase Locked Loop (PLL) is intrinsic to the operation of the
AD9753 in that it produces the necessary internally synchronized
2× clock for the edge-triggered latches, multiplexer, and DAC.
With PLLVDD connected to its supply voltage, the AD9753 is
in PLL ACTIVE mode. Figure 6 shows a functional block dia-
gram of the AD9753 clock control circuitry with PLL active.
The circuitry consists of a phase detector, charge pump, voltage
controlled oscillator (VCO), input data rate range control, clock
logic circuitry, and control input/outputs. The ÷ 2 logic in the
feedback loop allows the PLL to generate the 2× clock needed
for the DAC output latch.
CLKVDD
(3.1V TO 3.5V) PLLLOCK
392⍀ 1.0F
LPF PLLVDD
3.1V TO
3.5V
CLK+
CLK–
DIFFERENTIAL-
TO-
SINGLE-ENDED
AMP
PHASE
DETECTOR
TO INPUT
LATCHES
AD9753
CHARGE
PUMP
VCO
RANGE
CONTROL
(،1, 2, 4, 8)
،2
TO DAC
LATCH
CLKCOM
DIV0
DIV1
Figure 6. Clock Circuitry with PLL Active
Figure 7 defines the input and output timing for the AD9753
with the PLL active. CLK in Figure 25 represents the clock
which is generated external to the AD9753. The input data at
both Ports 1 and 2 is latched on the same CLK rising edge.
CLK may be applied as a single-ended signal by tying CLK– to
midsupply and applying CLK to CLK+, or as a differential
signal applied to CLK+ and CLK–.
RESET has no purpose when using the internal PLL and should
be grounded. When the AD9753 is in PLL ACTIVE mode,
PLLLOCK is the output of the internal phase detector. When
locked, the lock output in this mode will be a Logic “1.”
tS
tH
PORT 1
DATA IN
PORT 2
DATA X
DATA Y
CLK
IOUTA OR IOUTB
t LPW
1/2 CYCLE + tPD
a.
t PD
DATA X
DATA Y
PORT 1
DATA IN
PORT 2
DATA W
DATA X
DATA Y
DATA Z
CLK
IOUTA OR IOUTB
XXX
DATA W DATA X
DATA Y DATA Z
b.
Figure 7. DAC Input Timing Requirements with PLL Active
Typically, the VCO can generate outputs of 100 MHz to 400 MHz.
The range control is used to keep the VCO operating within its
designed range, while allowing input clocks as low as 6.25 MHz.
With the PLL active, logic levels at DIV0 and DIV1 determine
the divide (prescaler) ratio of the range controller. Table I gives
the frequency range of the input clock for the different states of
DIV0 and DIV1.
Table I. CLK Rates for DIV0, DIV1 Levels With PLL Active
CLK Frequency
50 MHz–150 MHz
25 MHz–100 MHz
12.5 MHz–50 MHz
6.25 MHz–25 MHz
DIV1
0
0
1
1
DIV0
0
1
0
1
Range Controller
÷1
÷2
÷4
÷8
A 392 Ω resistor and 1.0 µF capacitor connected in series from
LPF to PLLVDD are required to optimize the phase noise vs.
settling/acquisition time characteristics of the PLL. To obtain
optimum noise and distortion performance, PLLVDD should
be set to a voltage level similar to DVDD and CLKVDD.
In general, the best phase noise performance for any PLL range
control setting is achieved with the VCO operating near its
maximum output frequency of 400 MHz.
–10–
REV. 0
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