AD9985BSTZ-110 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9985BSTZ-110 Datasheet PDF : 32 Pages
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AD9985
SOG
HSYNC IN
SYNC STRIPPER
NEGATIVE PEAK
CLAMP
ACTIVITY
DETECT
COAST
ACTIVITY
DETECT
COMP
SYNC
MUX 1
SYNC SEPARATOR
INTEGRATOR
1/S
VSYNC
SOG OUT
PLL
POLARITY
DETECT
HSYNC
MUX 2
COAST
CLOCK
GENERATOR
HSYNC OUT
PIXEL CLOCK
HSYNC OUT
MUX 3
POLARITY
DETECT
AD9985
VSYNC IN
ACTIVITY
DETECT
POLARITY
DETECT
MUX 4
VSYNC OUT
Figure 14. Sync Processing Block Diagram
Table 43. Control of the Sync Block Muxes via the Serial Register
Serial Bus
Control
Mux No.
Control Bit
Bit State
Result
1 and 2
0EH: Bit 3
0
Pass Hsync
1
Pass Sync-on-Green
3
0FH: Bit 5
0
Pass Coast
1
Pass Vsync
4
0EH: Bit 0
0
Pass Vsync
1
Pass Sync Separator Signal
SYNC SLICER
The purpose of the sync slicer is to extract the sync signal from
the Green graphics channel. A sync signal is not present on all
graphics systems, only those with Sync-on-Green. The sync
signal is extracted from the Green channel in a two-step
process. First, the SOG input is clamped to its negative peak
(typically 0.3 V below the black level). Next, the signal goes to a
comparator with a variable trigger level, nominally 0.15 V above
the clamped level. The “sliced” sync is typically a composite sync
signal containing both Hsync and Vsync.
SYNC SEPARATOR
A sync separator extracts the Vsync signal from a composite
sync signal. It does this through a low-pass filter-like or
integrator-like operation. It works on the idea that the Vsync
signal stays active for a much longer time than the Hsync signal,
so it rejects any signal shorter than a threshold value, which is
somewhere between an Hsync pulsewidth and a Vsync
pulsewidth.
The sync separator on the AD9985 is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the
polarity of the composite sync signal. (Polarities are determined
elsewhere on the chip.) The basic idea is that the counter counts
up when Hsync pulses are present. But since Hsync pulses are
relatively short in width, the counter only reaches a value of N
before the pulse ends. It then starts counting down, eventually
reaching 0 before the next Hsync pulse arrives. The specific
value of N will vary for different video modes, but will always
be less than 255. For example, with a 1 µs width Hsync, the
counter will only reach 5 (1 µs/200 ns = 5). When Vsync is
present on the composite sync, the counter will also count up.
However, since the Vsync signal is much longer, it will count to
a higher number M. For most video modes, M will be at least
255. So, Vsync can be detected on the composite sync signal by
detecting when the counter counts to higher than N. The
specific count that triggers detection (T) can be programmed
through the serial register (11H).
Once Vsync has been detected, there is a similar process to
detect when it goes inactive. At detection, the counter first resets
to 0, then starts counting up when Vsync goes away. Similar to
the previous case, it will detect the absence of Vsync when the
counter reaches the threshold count (T). In this way, it will
reject noise and/or serration pulses. Once Vsync is detected to
be absent, the counter resets to 0 and begins the cycle again.
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