POWER SUPPLY MONITOR
The ADE7762 contains an on-chip power supply monitor. The
power supply (VDD) is monitored continuously. At power-up,
when the supply is less than 4 V ± 2% and VREF is less than 1.9 V
(typical), the outputs of the ADE7762 are inactive and the data
path is held in reset. Once VDD is greater than 4 V ±2% and
VREF is greater than 1.9 V (typical), the chip is active and energy
accumulation begins. At power-down, when VDD falls below
4 V or VREF falls below 1.9 V (typical), the data path is again held
in reset. This implementation ensures correct device operation
at power-up and at power-down. The power supply monitor
has built-in hysteresis and filtering. This gives a high degree of
immunity to false triggering due to noisy supplies.
The power supply and decoupling for the part should be such
that the ripple at VDD does not exceed ±5% as specified for
normal operation.
ADE7762
5V
4V
2.4V
1.9V
0V
VDD
VREF
INTERNAL
RESET
INACTIVE
ACTIVE
INACTIVE
Figure 20. On-Chip Power Supply Monitor
Rev. 0 | Page 17 of 28