ADE3700SX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3700SX Datasheet PDF : 89 Pages
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ADE3700
Sync Retiming (SRT)
2.5 Sync Retiming (SRT)
The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into
the XCLK and INCLK domains.
For the XCLK domain, the SRT has the following functions:
q Retimes all sync signals going to SMEAS into the XCLK domain.
q Extracts the vertical sync signal from composite sync signals (AHSYNC and ACSYNC pins)
q Divides clocks by 1024 for activity detection purposes.
q Generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source.
q Generates a coast signal in the XCLK domain for the LLPLL.
Table 8: Sync Retiming Registers (Sheet 1 of 2)
Register Name
SRTXK_CSYNC_INV
SRTXK_SOG_THR_L
SRTXK_SOG_THR_H
SRTXK_CSYNC_THR_L
SRTXK_CSYNC_THR_H
SRTXK_VSYNC_SEL
SRTXK_VSYNC_THR_L
SRTXK_VSYNC_THR_H
Addr
0x01E0
0x01E1
0x01E2
0x01E3
0x01E4
0x01E5
0x01E6
0x01E7
Mode Bits
[7:3]
R/W
[2]
R/W
[1]
R/W
[0]
R/W
[7:0]
R/W
[7:4]
[3:0]
R/W
[7:0]
R/W
[7:4]
[3:0]
R/W
[7:3]
[2:0]
R/W
[7:0]
R/W
[7:4]
R/W
[3:0]
Default
Description
0x0
0x0
0x0
0x0
0x080
0x080
0x0
0x080
Reserved
invert filtered vert sync signal
invert composite sync signal
invert SOG signal
SOG vert sync extractor threshold [7:0]
Reserved
SOG vert sync extractor threshold [11:8]
composite sync vertical sync extractor
threshold [7:0]
Reserved
composite sync vertical sync extractor
threshold [11:8]
Reserved
filtered vert sync source select
0x0: avsync pin
0x1: vsync from composite ahsync pin
0x2: vsync from composite acsync pin
0x3: Reserved
0x4 - 0x7: Reserved
filtered vert sync delay [7:0]
Reserved
filtered vert sync delay [11:8]
23/89
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