ADE3300 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3300 Datasheet PDF : 88 Pages
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ADE3XXX
Line Lock PLL Block
2.4 Line Lock PLL Block
The line lock PLL recovers a sample clock from an incoming hsync source. The response
characteristics of the line lock PLL are adjustable for optimimum response time and jitter filtering.
The phase of the sample clock is digitally adjustable by steps of 289 ps (with a 27-MHz crystal). The
I2C interface of the line lock PLL is in the LLK_CTRL clock domain which must be active for
programming.
The PLL loop filter has three ranges with independent filter parameters. When the phase detector
error remains below a programmable threshold for a programmable number of input lines, the loop
filter coefficients change. Any phase detector error above the programmed threshold reverts the
filter to the appropriate level in one line. The operation is represented in Figure 3.
Figure 3: Line Lock PLL State Diagram
error <= SLOW_TOL for
more than SLOW_LINE_NB
of lines
error <= LOCK_TOL for
more than LOCK_LINE_NB
of lines
fast
slow
lock
error > SLOW_TOL
error > LOCK_TOL
The digital loop filter is controlled by three parameters: MFACTOR, A and B. M_FACTOR is the
desired number of clocks per input line. The A and B parameters control the response of the 2nd
order digital filter. A and B are composed of a linear and exponential component designated by the
L and E suffix, respectively. These numbers are related to the classic 2nd order damping and
natural frequency as follows:
Damping = AL x 2(AE-12) x SQRT(5 x M_FACTOR / (BL x 2BE))
Natural Frequency = SQRT(M_FACTOR x 5 x BL x 2(BE-34))
Register Name
LLK_PLL_CLEAR
Table 7: Line Lock PLL Registers (Sheet 1 of 4)
Addr
0x0800
Mode Bits
[7:6]
R/W
[5]
R/W
[4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
Default
Description
Reserved
0x0
Master Reset
0x0
Reset the PLL synthetic sync
0x0
Reset PLL offset
0x0
Reset PLL accumulator
0x0
Reset the low pass filter
0x0
Reset the PLL phase error
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