ADE3300 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3300 Datasheet PDF : 88 Pages
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Digital Video Input (DVI)
ADE3XXX
Table 7: Line Lock PLL Registers (Sheet 4 of 4)
Register Name
LLK_PLL_UPDATE
LLK_PLL_STATUS
LLK_PLL_PH_ERROR_L
LLK_PLL_PH_ERROR_H
LLK_PLL_PHASE_RATE_0
LLK_PLL_PHASE_RATE_1
LLK_PLL_PHASE_RATE_2
LLK_PLL_PHASE_RATE_3
LLK_PLL_PHASE_RATE_I_0
LLK_PLL_PHASE_RATE_I_1
LLK_PLL_PHASE_RATE_I_2
LLK_PLL_PHASE_RATE_I_3
LLK_PLL_STAT_ERROR_MEAN
LLK_PLL_STAT_ERROR_PP_L
LLK_PLL_STAT_ERROR_PP_H
LLK_PLL_STAT_ERROR_ABS_L
LLK_PLL_STAT_ERROR_ABS_H
LLK_PLL_STAT_ERROR_GTX
Addr
0x0840
0x0841
0x0842
0x0843
0x0844
0x0845
0x0846
0x0847
0x0848
0x0849
0x084A
0x084B
0x084C
0x084D
0x084E
0x084F
0x0850
0x0851
Mode Bits
R
[7]
[6:2]
R/W
[1]
R/W
[0]
[7:4]
R
[3]
R
[2]
R
[1]
R
[0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
R
[7:0]
[7:0]
Default
Description
In Free-running mode, toggles when status
is updated.
In one-shot mode, this bit is set when status
is ready.
Reserved
0x0
0: Free-running mode
1: one-shot mode
0x0
update enable
Reserved
LLK overflow
coarse error = 0
in slow mode
in lock mode
phase error
LSB = approx. 200ps
LLK phase rate
fOUT = fXTAL x 227+NDIV / PHASE_RATE
integral phase rate
Average Phase Error over STAT_LINES
phase error LSB is approx. 200ps
Peak Phase Error over STAT_LINES
phase error LSB is approx. 200ps
sum of absolute phase errors over
STAT_LINES
phase error LSB is approx. 200ps
Reserved
2.5 Digital Video Input (DVI)
The DVI receiver has the following features:
q compatible with all DVI complaint transmitters up to 140 MHz pixel clock
q on chip termination adjustable by I2C and/or one (~10X) external reference resistor
q HDCP and standby / power down supported
q decoder digitally corrects for skew errors of at least ±1 pixel in reference to any other channel
q bitstream can be decoded and measured without the presence of horizontal and vertical sync
pulses
22/88
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