ADE3300 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3300

LCD Display Engines with Integrated DVI, ADC and YUV Ports

STMicroelectronics 

ADE3XXX

Scaler Block

PNL block to the LCD gamma value, then the post-scaler gamma RAM implements the

corresponding inverse gamma function.

Table 17: PNL Registers

Register Name

PNL_CTRL

Addr

0x0080

Mode Bits

R/W

[7:6]

[5:0]

Default

Description

0x0

Reserved

0x0

0x00: bypass

0x01 - 0x1F: gamma <1.0

0x20 - 0x3F: gamma >1.0

0x30: gamma = 2.2

2.14

Scaler Block

The scale module resizes images from one resolution to another. For this, a 3x3 non-separable

scaling filter performs a dot product of the input pixel values with a weighting vector computed from

the chosen filtering function. To sharpen text without introducing excessive artifacts, the output pixel

contrast level is adjusted with the context value measured over a 3x3 grid in the relevant area of the

source image.

For proper scaler operation, set the SCLK frequency to be greater than the max of dclk and

in_hpixel x dclk_freq / (dest_hpixel x pixel_avg).

Table 18: Scaler Block Registers (Sheet 1 of 3)

Register Name

SCL_SRC_HPIX_L

SCL_SRC_HPIX_H

SCL_SRC_VPIX_L

SCL_SRC_VPIX_H

SCL_DES_HPIX_L

SCL_DES_HPIX_H

SCL_DES_VPIX_L

SCL_DES_VPIX_H

SCL_HPOS_L

SCL_HPOS_H

SCL_VPOS_E_L

SCL_VPOS_E_H

SCL_VPOS_O_L

SCL_VPOS_O_H

SCL_THRES_SLOPE

Addr

0x0A00

0x0A01

0x0A02

0x0A03

0x0A04

0x0A05

0x0A08

0x0A09

0x0A0A

0x0A0B

0x0A0E

0x0A0F

0x0A10

0x0A11

0x0A12

Mode Bits

R/W

[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:6]

[5:0]

Default

Description

0x0

input horizontal resolution in top 12 bits

Bits [3:0] must be set to zero.

If pixel averaging is necessary then this

register contains the averaged, round-down

resolution, e.g, if the original resolution is 65

and if the mode is averaging-by-2 then 32

should be programmed in this register.

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x28

Input Vertical Resolution

[3:0] must be set to 0.

scaled active area width in pixels

[15:4] = integer; [3:0] = fraction

scaled active area height in lines

[15:4] = integer; [3:0] = fraction

horizontal position of upper left pixel of active

output data

[15:4] = integer; [3:0] = fraction

vertical position of upper left pixel of output

data for even/non-interlace frames

[15:4] = integer; [3:0] = fraction

vertical position of the upper left pixel of

output data of odd fields

bits [15:4] = integer; bits [3:0] = fraction

Reserved

slope of the contrast amplification function

49/88

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