General Description
ADE3800
Table 2: ADE3800 Block Descriptions
Block
Output Mux (OMUX)
Timing Controller (TCON)
LVDS/RSDS Features
Pulse Width Modulation (PWM)
I²C Block Transfer (I2CBKT)
I²C Registers and RAM Addresses
Description
An extension of the ADE3700 output mux block. The major changes are:
- LVDS controls
- RSDS split line buffer
Provides timing for Smart Panel applications and other applications that are sensitive to
output synchronization timing. The timing unit is based on horizontal and vertical counters,
which are locked with the output video stream.
Has the following features:
- Power down
- Output swing and common mode programmable
- Individual channel programmable delay
- Programmable LVDS clock output polarity
Generates two signals that can be used to control backlight inverter switching power
components directly. It is derived from XCLK and can be powered up independently of the
DOTCLK and INCLK domains.
Allows the internal I2C parallel bus to be driven by an xclk state machine to perform rapid
block transfers between internal addresses.
Memory mapping of all RAM and register locations accessible by I²C.
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