ADE3800
8 ADE3800 vs ADE3700
ADE3800 vs ADE3700
The following gives an overview of the main differences between ADE3700 and ADE3800:
Package
● 100 pin LQFP for LVDS 1&2 channels and RSDS 1 channel application
● 128 pin LQFP for RSDS 2 pixel per clock support
● 5V tolerant inputs do not have internal pull-up resistors
I2C Interface
● Add Block Transfer for fast internal data move/swap/copy
Registers
● Now all registers runs on XCLK
● RGB register address ordering is reversed to BGR
Analog Front End (ADC & SOG)
● New ADC design with higher performances
● Add Internal SOG Sync Stripper with bypass option (external SOG TTL pin)
● SOG activity can operate while ADC Power is down (wakeup from DPMS by SOG support)
● Per channel skew control
● Analog Filter bandwidth programmable
● Gain and Offset independent and linear
● 10-bit ADC using Analog Dithering Technique (ADTH)
Line Lock PLL (LLK)
● Synthesized Internal HSync has 50% duty cycle
● Phase step is 4 times more precise
● Phase range can exceed one clock period delay
● Lock filter removed
● Fewer registers, simplifies some programming
● Clock and Phase are both shadowed
● FM Modulation amplitude step is 16 times more precise
Sync Measurement (SMEAS)
● Remove out of range register
● Add Fast Mute function
● Group all the fast mute flags in SMEAS with sticky bit and enable
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