Glossary
9 Glossary
ADE3800
AFE
Analog Front End, this includes the ADC and SOG circuitries
Bare Panel see Smart Panel
bpp
bit per pixels (OSD Font: 4bpp = 16 color characters)
DFT
in_enab
design For Test block to output certain internal signals (otherwise not available)
in_henab & in_venab = Input active area signal*
in_henab
input horizontal active pixel signal*
in_venab
input vertical active line signal*
LVDS
out_enab
low voltage differential signaling video interface to LCD panel
out_henab & out_venab = Output panel active area signal*
out_henab output panel horizontal active pixel signal*
out_venab
ppc
output panel vertical active line signal*
pixels per clock (2 ppc = dual wide panel bus interface)
PVT
parameters that depend on Process (chip), Voltage (power) and Temperature
(board)
RSDS
SIP Panel
reduced swing differential signaling video interface to LCD panel
see Smart Panel
Smart Panel
SOG
panel without built-in TCON using TTL or RSDS input video interface, additional
timing signals must be provided for proper operation.
sync on Green type signal
sRGB
standard RGB, color matching between display and real life
SRTD
Set-Reset-Toggle-Delay programmable gate in TCON
Standard Panel panel with built-in TCON using LVDS or TTL input video interface
TCON
timing controller function
TMDS
transition minimized differential signaling video interface from DVI digital video
input
* All enab type signals are active high
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