ADE3800SXT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3800SXT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

Register Description by Block

4 Register Description by Block

ADE3800

4.1 Global Control (GLBL)

The Global Control block is responsible for:

● Selecting clock sources

● Power control

● I²C control

● Block by block synchronous reset generation.

The global control block runs in the crystal clock (XCLK) domain, which is required to be active for

programming. In general for all ADE3800 blocks, I²C register access operates in the XCLK domain;

exceptions are the internal RAMS which require the appropriate clock domain to be active (e.g.

dotclk for OSD RAMs), refer to Table 44.

Table 9: Global Control Registers (Sheet 1 of 3)

Register Name

Addr Mode Bits

GLBL_REV_ID

0000 R

[7:0]

GLBL_CLK_SRC_SEL_0 0001 R/W [6:4]

[2:0]

GLBL_CLK_SRC_SEL_1 0002 R/W [6:4]

[2:0]

Rst

Description

0x83

00

00

REV_ID: Chip Revision ID

DOTCLK_SRC_SEL: DOTCLK source select

0: Crystal Clock

1: XCLK pin (test only)

2: FM freq synth half speed (1 ppc) a

3: FM freq synth full speed (2 ppc) 1

4: SCLK frequency synthesizer

5-7: Reserved

INCLK_SRC_SEL: input clock source select

0: Crystal Clock

1: XCLK pin (test only)

2: LLPLL phase controlled SRC (normal)

3: LLPLL fixed phase clock (test only)

4: LLPLL control clock (test only)

5-7: Reserved

OUTCLK_SRC_SEL: panel output clock source select

0: Crystal Clock

1: XCLK pin (test only)

2: FM freq synth half speed (1 ppc) b

3: FM freq synth full speed (2 ppc) 1

4: SCLK frequency synthesizer

5-7: Reserved

SCLK_SRC_SEL: scaler clock source select

0: crystal clock

1: XCLK pin (test only)

2: FM freq synth half speed

3: FM freq synth full speed

4: Fixed freq synth (normal)

5: LVDS pll output (test only)

6: LVDS pll input (test only)

7: Reserved

18/138

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