ADE3800
Register Description by Block
Register Name
DMEAS_DATA_0
DMEAS_DATA_1
DMEAS_DATA_2
DMEAS_DATA_3
DMEAS_DATA_4
DMEAS_DATA_5
DMEAS_DATA_6
DMEAS_DATA_7
Table 21: DMEAS Registers (Sheet 3 of 3)
Addr Mode Bits Rst
Description
090E R
090F R
0910 R
0911 R
0912 R
0913 R
0914 R
0915 R
[7:0]
00
Refer to Table 22 below
[7:0]
00
[7:0]
00
[7:0]
00
[7:0]
00
[7:0]
00
[7:0]
00
[7:0]
00
Table 22: DMEAS Output Registers Assignment
alg_sel = 00
alg_sel = 01
alg_sel = 10
alg_sel = 11
DMEAS_DATA_0 edge_out [7:0]
min_out [7:0]
hpos_min [7:0]
de_size_out [7:0]
DMEAS_DATA_1 edge_out [15:8]
DMEAS_DATA_2 edge_out [23:16]
max_out [7:0]
pcd_out [7:0]
hpos_min [11:8]
hpos_max [7:0]
de_size_out [15:8]
de_mismatch_flag
DMEAS_DATA_3 edge_out [31:24] pcd_out [15:8]
hpos_max [11:8] N/A
DMEAS_DATA_4 psum_out [7:0]
DMEAS_DATA_5 psum_out [15:8]
pcd_out [23:16] vpos_min [7:0]
N/A
N/A
vpos_min [11:8] N/A
DMEAS_DATA_6 psum_out [23:16] N/A
vpos_max [7:0]
N/A
DMEAS_DATA_7 psum_out [31:24] N/A
vpos_max [11:8] N/A
4.10 Scale (SCL)
ADE scales input video to output panel resolution without external video frame memory. This
requires tuning of the panel timing parameters to make the vertical active time match the panel’s.
Features:
● Separable 3V x 4H polyphase filter:
— 3 line filter for H resolutions <= 1024
— 2 line filter for H resolutions > 1024
● independent H & V kernel register storage
— 64 phases are interpolated from 6V or 10H reference points
— symmetric kernels only
— coefficients range from –2 to +1 63/64
● Simple pointer collision feedback mechanism
● 2-way 3rd generation context sensitive filtering
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