ADE3800SXL View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3800SXL
STMicroelectronics
ADE3800SXL Datasheet PDF : 138 Pages
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Register Description by Block
ADE3800
● Background color management
For formulae to program the registers refer to Chapter 7: Scaler Equations on page 132.
4.10.1 Frame Synchronization
Due to the limited pixel memory of the chip, the output active video needs to be perfectly
synchronized with the input active video. This mode of operation is called Frame Lock.
Figure 9: Frame Lock Operation
Register Name
SCL_SRC_HPIX_L
SCL_SRC_HPIX_U
SCL_SRC_VPIX_L
SCL_SRC_VPIX_U
SCL_SCALEFACH_L
SCL_SCALEFACH_M
SCL_SCALEFACH_U
SCL_SCALEFACV_L
SCL_SCALEFACV_M
SCL_SCALEFACV_U
SCL_ORIGHPOS_L
SCL_ORIGHPOS_U
SCL_ORIGVPOS_L
SCL_ORIGVPOS_U
SCL_PIPE_RATE_L
SCL_PIPE_RATE_U
Table 23: Scale Registers (Sheet 1 of 3)
Addr
0A00
0A01
0A02
0A03
0A04
0A05
0A06
0A07
0A08
0A09
0A0A
0A0B
0A0C
0A0D
0A0E
R/W Bits Rst
R/W [7:0] 00
R/W [3:0] 00
R/W [7:0] 00
R/W [3:0] 00
R/W [7:0] 00
R/W [7:0] 00
R/W [0]
00
R/W [7:0] 00
R/W [7:0] 00
R/W [0]
00
R/W [7:0] 00
R/W [7:0] 00
R/W [7:0] 00
R/W [7:0] 00
R/W [7:0] 00
Description
input horizontal resolution
input vertical resolution
17-bit horizontal scale factor
17-bit vertical scale factor
2’s complement , signed number
27-bit horizontal position of the first output pixel
2’s complement , signed number
27-bit vertical position of the first output pixel
Programmable update rate, which controls when a new
pixel column is read out of the line buffer.
For (sclk==dotclk) && (dest_hpix == in_hpix), pipe_rate =
0.
0A0F R/W [3:0] 00
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