ADE3800XT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3800XT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

Register Description by Block

ADE3800

HBLOCK_SIZE

FRAME_CNT_MAX

0CA2

0CA3

WF_SHIFT

FLICKER_MEAS0

FLICKER_MEAS1

FLICKER_MEAS2

FLICKER_MEAS3

0CA4

0CB1 – B4

0CB5 – B8

0CB9 – BC

0CBD – C0

Table 31: FLK Registers (Sheet 2 of 2)

R/W [3:0] 00 Size in bits of horizontal window = 2 ^ (3+ hblock_size)

R/W [7:0] 08 -Number of frames to complete one measurement

-Total number of pixs in a line would be:

frame_cnt_max * (2 ^ (3+ hblock_size) )

-example: hblock_size = 0; frame_cnt_max = 8;

means that it will take 8 frames to finish the calculation. For

each frame only one portion of the image is being calculated

on. The size of that portion is 2 ^ (3 + hblock_size), in this

case 8 pixels. This means that the calculated line length = 8

pix window * 8 frames = 64 pixels

R/W [2:0] 00 Selector of which 4 of the Walsh function is measuring

R/W [31:0] 00 Score reg showing pattern matching pattern 0

R/W [31:0] 00 Score reg showing pattern matching pattern 1

R/W [31:0] 00 Score reg showing pattern matching pattern 2

R/W [31:0] 00 Score reg showing pattern matching pattern 3

4.16 Adaptive Phase Control (APC)

The APC block generates a 2-bit dither pattern for an 8-bit panel or a 4-bit dither pattern for a 6-bit

panel to visually improve the amplitude resolution of the 10-bit RGB output signal.

4.16.1 Function

The heart of the APC block consists of a 32x32x4 bit lookup table (LUT). It represents one threshold

matrix, which can be read using a programmable addressing technique as well as a programmable

dither threshold control. The panel depth APC_CTRL0[1] should match the bit depth of the panel

and is not masked by APC enable APC_CTRL0[0]. When APC_CTRL0[0] is cleared, the dither

pattern is set to zero.

4.16.2 Addressing Technique

The APC block offers an I2C programmable addressing technique to generate various temporal

dither patterns. The frame offset APC_CTRL1[7:4] is a 4-bit increment value, which defines the

horizontal/vertical displacement of the dither matrix from frame to frame. After the frame length

APC_CTRL1[3:0] + 1 number of frames, both horizontal and vertical displacement positions will be

reset to zero, only when the frame length APC_CTRL1[3:0] > 0.

Note: To set the frame accumulator to zero, the frame offset APC_CTRL1[7:4] must be programmed to 0,

and the frame length APC_CTRL1[3:0] to 1.

The frame offset can be independently activated in the horizontal and vertical dimension using

respectively APC_CTRL0[5] and APC_CTRL0[6]. In addition, APC_CTRL0[7] enables a horizontal

displacement increment of the frame offset APC_CTRL1[7:4] per color component.

4.16.3 Dither threshold Control

When the panel depth APC_CTRL0[1] is set to 0, the 4-bit LUT output value maps to a 2-bit value

for 8-bit panels.

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